Project home: https://bues.ch Original repository at: https://git.bues.ch/git/crcgen.git

Michael Buesch 00f6a04d45 Bump version 1 month ago
crcgen 00f6a04d45 Bump version 1 month ago
maintenance d35c08a0ff Add build framework 11 months ago
scripts 1e8118161a main: Remove unnecessary call to main() 11 months ago
.gitignore cca0da812c Update .gitignore 11 months ago
COPYING 55e6f6b691 Initial commit 11 months ago
MANIFEST.in d35c08a0ff Add build framework 11 months ago
README.rst d35c08a0ff Add build framework 11 months ago
crcgen_test.py f8c7c21d28 Fix crash for one optimization combination 1 month ago
setup.py a456290201 Add crcgen main script 11 months ago

README.rst

CRC algorithm code generator
============================

This tool generates synthesizable Verilog code for use in FPGAs to calculate CRC (Cyclic Redundancy Check) checksums.


License
=======

Copyright (c) 2019 Michael Buesch

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.