Project home: https://bues.ch Original repository at: https://git.bues.ch/git/crcgen.git

Michael Buesch 1e8118161a main: Remove unnecessary call to main() 3 months ago
crcgen 1e8118161a main: Remove unnecessary call to main() 3 months ago
maintenance d35c08a0ff Add build framework 3 months ago
scripts 1e8118161a main: Remove unnecessary call to main() 3 months ago
.gitignore cca0da812c Update .gitignore 3 months ago
COPYING 55e6f6b691 Initial commit 4 months ago
MANIFEST.in d35c08a0ff Add build framework 3 months ago
README.rst d35c08a0ff Add build framework 3 months ago
crcgen_test.py 27da987052 test: Add 64bit coefficients 3 months ago
setup.py a456290201 Add crcgen main script 3 months ago

README.rst

CRC algorithm code generator
============================

This tool generates synthesizable Verilog code for use in FPGAs to calculate CRC (Cyclic Redundancy Check) checksums.


License
=======

Copyright (c) 2019 Michael Buesch

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.