README.rst 1.3 KB

  1. CRC algorithm code generator
  2. ============================
  3. This tool generates synthesizable Verilog, VHDL or MyHDL code for use in FPGAs to calculate CRC (Cyclic Redundancy Check) checksums.
  4. Example usage
  5. =============
  6. Display all options:
  7. .. code:: sh
  8. crcgen -h
  9. Generate Verilog code for CRC-32:
  10. .. code:: sh
  11. crcgen -a CRC-32 -v
  12. Generate VHDL code for CRC-32:
  13. .. code:: sh
  14. crcgen -a CRC-32 -V
  15. Generate Verilog code for a custom non-standard CRC or any standard algorithm that's not included in crcgen's -a list:
  16. .. code:: sh
  17. crcgen -P "x^8 + x^7 + x^5 + x^4 + x^2 + x + 1" -B16 -R -v
  18. License
  19. =======
  20. Copyright (c) 2019-2021 Michael Buesch <>
  21. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
  22. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
  23. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.