cpu.c 6.9 KB

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  1. // Copyright 2011 Google Inc. All Rights Reserved.
  2. //
  3. // Use of this source code is governed by a BSD-style license
  4. // that can be found in the COPYING file in the root of the source
  5. // tree. An additional intellectual property rights grant can be found
  6. // in the file PATENTS. All contributing project authors may
  7. // be found in the AUTHORS file in the root of the source tree.
  8. // -----------------------------------------------------------------------------
  9. //
  10. // CPU detection
  11. //
  12. // Author: Christian Duvivier (cduvivier@google.com)
  13. #include "./dsp.h"
  14. #if defined(WEBP_HAVE_NEON_RTCD)
  15. #include <stdio.h>
  16. #include <string.h>
  17. #endif
  18. #if defined(WEBP_ANDROID_NEON)
  19. #include <cpu-features.h>
  20. #endif
  21. //------------------------------------------------------------------------------
  22. // SSE2 detection.
  23. //
  24. // apple/darwin gcc-4.0.1 defines __PIC__, but not __pic__ with -fPIC.
  25. #if (defined(__pic__) || defined(__PIC__)) && defined(__i386__)
  26. static WEBP_INLINE void GetCPUInfo(int cpu_info[4], int info_type) {
  27. __asm__ volatile (
  28. "mov %%ebx, %%edi\n"
  29. "cpuid\n"
  30. "xchg %%edi, %%ebx\n"
  31. : "=a"(cpu_info[0]), "=D"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])
  32. : "a"(info_type), "c"(0));
  33. }
  34. #elif defined(__x86_64__) && \
  35. (defined(__code_model_medium__) || defined(__code_model_large__)) && \
  36. defined(__PIC__)
  37. static WEBP_INLINE void GetCPUInfo(int cpu_info[4], int info_type) {
  38. __asm__ volatile (
  39. "xchg{q}\t{%%rbx}, %q1\n"
  40. "cpuid\n"
  41. "xchg{q}\t{%%rbx}, %q1\n"
  42. : "=a"(cpu_info[0]), "=&r"(cpu_info[1]), "=c"(cpu_info[2]),
  43. "=d"(cpu_info[3])
  44. : "a"(info_type), "c"(0));
  45. }
  46. #elif defined(__i386__) || defined(__x86_64__)
  47. static WEBP_INLINE void GetCPUInfo(int cpu_info[4], int info_type) {
  48. __asm__ volatile (
  49. "cpuid\n"
  50. : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])
  51. : "a"(info_type), "c"(0));
  52. }
  53. #elif (defined(_M_X64) || defined(_M_IX86)) && \
  54. defined(_MSC_FULL_VER) && _MSC_FULL_VER >= 150030729 // >= VS2008 SP1
  55. #include <intrin.h>
  56. #define GetCPUInfo(info, type) __cpuidex(info, type, 0) // set ecx=0
  57. #elif defined(WEBP_MSC_SSE2)
  58. #define GetCPUInfo __cpuid
  59. #endif
  60. // NaCl has no support for xgetbv or the raw opcode.
  61. #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
  62. static WEBP_INLINE uint64_t xgetbv(void) {
  63. const uint32_t ecx = 0;
  64. uint32_t eax, edx;
  65. // Use the raw opcode for xgetbv for compatibility with older toolchains.
  66. __asm__ volatile (
  67. ".byte 0x0f, 0x01, 0xd0\n"
  68. : "=a"(eax), "=d"(edx) : "c" (ecx));
  69. return ((uint64_t)edx << 32) | eax;
  70. }
  71. #elif (defined(_M_X64) || defined(_M_IX86)) && \
  72. defined(_MSC_FULL_VER) && _MSC_FULL_VER >= 160040219 // >= VS2010 SP1
  73. #include <immintrin.h>
  74. #define xgetbv() _xgetbv(0)
  75. #elif defined(_MSC_VER) && defined(_M_IX86)
  76. static WEBP_INLINE uint64_t xgetbv(void) {
  77. uint32_t eax_, edx_;
  78. __asm {
  79. xor ecx, ecx // ecx = 0
  80. // Use the raw opcode for xgetbv for compatibility with older toolchains.
  81. __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
  82. mov eax_, eax
  83. mov edx_, edx
  84. }
  85. return ((uint64_t)edx_ << 32) | eax_;
  86. }
  87. #else
  88. #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains.
  89. #endif
  90. #if defined(__i386__) || defined(__x86_64__) || defined(WEBP_MSC_SSE2)
  91. // helper function for run-time detection of slow SSSE3 platforms
  92. static int CheckSlowModel(int info) {
  93. // Table listing display models with longer latencies for the bsr instruction
  94. // (ie 2 cycles vs 10/16 cycles) and some SSSE3 instructions like pshufb.
  95. // Refer to Intel 64 and IA-32 Architectures Optimization Reference Manual.
  96. static const uint8_t kSlowModels[] = {
  97. 0x37, 0x4a, 0x4d, // Silvermont Microarchitecture
  98. 0x1c, 0x26, 0x27 // Atom Microarchitecture
  99. };
  100. const uint32_t model = ((info & 0xf0000) >> 12) | ((info >> 4) & 0xf);
  101. const uint32_t family = (info >> 8) & 0xf;
  102. if (family == 0x06) {
  103. size_t i;
  104. for (i = 0; i < sizeof(kSlowModels) / sizeof(kSlowModels[0]); ++i) {
  105. if (model == kSlowModels[i]) return 1;
  106. }
  107. }
  108. return 0;
  109. }
  110. static int x86CPUInfo(CPUFeature feature) {
  111. int max_cpuid_value;
  112. int cpu_info[4];
  113. int is_intel = 0;
  114. // get the highest feature value cpuid supports
  115. GetCPUInfo(cpu_info, 0);
  116. max_cpuid_value = cpu_info[0];
  117. if (max_cpuid_value < 1) {
  118. return 0;
  119. } else {
  120. const int VENDOR_ID_INTEL_EBX = 0x756e6547; // uneG
  121. const int VENDOR_ID_INTEL_EDX = 0x49656e69; // Ieni
  122. const int VENDOR_ID_INTEL_ECX = 0x6c65746e; // letn
  123. is_intel = (cpu_info[1] == VENDOR_ID_INTEL_EBX &&
  124. cpu_info[2] == VENDOR_ID_INTEL_ECX &&
  125. cpu_info[3] == VENDOR_ID_INTEL_EDX); // genuine Intel?
  126. }
  127. GetCPUInfo(cpu_info, 1);
  128. if (feature == kSSE2) {
  129. return !!(cpu_info[3] & (1 << 26));
  130. }
  131. if (feature == kSSE3) {
  132. return !!(cpu_info[2] & (1 << 0));
  133. }
  134. if (feature == kSlowSSSE3) {
  135. if (is_intel && (cpu_info[2] & (1 << 0))) { // SSSE3?
  136. return CheckSlowModel(cpu_info[0]);
  137. }
  138. return 0;
  139. }
  140. if (feature == kSSE4_1) {
  141. return !!(cpu_info[2] & (1 << 19));
  142. }
  143. if (feature == kAVX) {
  144. // bits 27 (OSXSAVE) & 28 (256-bit AVX)
  145. if ((cpu_info[2] & 0x18000000) == 0x18000000) {
  146. // XMM state and YMM state enabled by the OS.
  147. return (xgetbv() & 0x6) == 0x6;
  148. }
  149. }
  150. if (feature == kAVX2) {
  151. if (x86CPUInfo(kAVX) && max_cpuid_value >= 7) {
  152. GetCPUInfo(cpu_info, 7);
  153. return !!(cpu_info[1] & (1 << 5));
  154. }
  155. }
  156. return 0;
  157. }
  158. VP8CPUInfo VP8GetCPUInfo = x86CPUInfo;
  159. #elif defined(WEBP_ANDROID_NEON) // NB: needs to be before generic NEON test.
  160. static int AndroidCPUInfo(CPUFeature feature) {
  161. const AndroidCpuFamily cpu_family = android_getCpuFamily();
  162. const uint64_t cpu_features = android_getCpuFeatures();
  163. if (feature == kNEON) {
  164. return (cpu_family == ANDROID_CPU_FAMILY_ARM &&
  165. 0 != (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON));
  166. }
  167. return 0;
  168. }
  169. VP8CPUInfo VP8GetCPUInfo = AndroidCPUInfo;
  170. #elif defined(WEBP_USE_NEON)
  171. // define a dummy function to enable turning off NEON at runtime by setting
  172. // VP8DecGetCPUInfo = NULL
  173. static int armCPUInfo(CPUFeature feature) {
  174. if (feature != kNEON) return 0;
  175. #if defined(__linux__) && defined(WEBP_HAVE_NEON_RTCD)
  176. {
  177. int has_neon = 0;
  178. char line[200];
  179. FILE* const cpuinfo = fopen("/proc/cpuinfo", "r");
  180. if (cpuinfo == NULL) return 0;
  181. while (fgets(line, sizeof(line), cpuinfo)) {
  182. if (!strncmp(line, "Features", 8)) {
  183. if (strstr(line, " neon ") != NULL) {
  184. has_neon = 1;
  185. break;
  186. }
  187. }
  188. }
  189. fclose(cpuinfo);
  190. return has_neon;
  191. }
  192. #else
  193. return 1;
  194. #endif
  195. }
  196. VP8CPUInfo VP8GetCPUInfo = armCPUInfo;
  197. #elif defined(WEBP_USE_MIPS32) || defined(WEBP_USE_MIPS_DSP_R2) || \
  198. defined(WEBP_USE_MSA)
  199. static int mipsCPUInfo(CPUFeature feature) {
  200. if ((feature == kMIPS32) || (feature == kMIPSdspR2) || (feature == kMSA)) {
  201. return 1;
  202. } else {
  203. return 0;
  204. }
  205. }
  206. VP8CPUInfo VP8GetCPUInfo = mipsCPUInfo;
  207. #else
  208. VP8CPUInfo VP8GetCPUInfo = NULL;
  209. #endif