mediatek-thermal.txt 1.8 KB

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  1. * Mediatek Thermal
  2. This describes the device tree binding for the Mediatek thermal controller
  3. which measures the on-SoC temperatures. This device does not have its own ADC,
  4. instead it directly controls the AUXADC via AHB bus accesses. For this reason
  5. this device needs phandles to the AUXADC. Also it controls a mux in the
  6. apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
  7. is also needed.
  8. Required properties:
  9. - compatible:
  10. - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
  11. - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
  12. - reg: Address range of the thermal controller
  13. - interrupts: IRQ for the thermal controller
  14. - clocks, clock-names: Clocks needed for the thermal controller. required
  15. clocks are:
  16. "therm": Main clock needed for register access
  17. "auxadc": The AUXADC clock
  18. - resets: Reference to the reset controller controlling the thermal controller.
  19. - mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
  20. - mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
  21. - #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description.
  22. Optional properties:
  23. - nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
  24. unspecified default values shall be used.
  25. - nvmem-cell-names: Should be "calibration-data"
  26. Example:
  27. thermal: thermal@1100b000 {
  28. #thermal-sensor-cells = <1>;
  29. compatible = "mediatek,mt8173-thermal";
  30. reg = <0 0x1100b000 0 0x1000>;
  31. interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
  32. clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
  33. clock-names = "therm", "auxadc";
  34. resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
  35. reset-names = "therm";
  36. mediatek,auxadc = <&auxadc>;
  37. mediatek,apmixedsys = <&apmixedsys>;
  38. nvmem-cells = <&thermal_calibration_data>;
  39. nvmem-cell-names = "calibration-data";
  40. };