gml4gtk/data/chip1.gv

/* vlsi chip design type of graph */
digraph o /* seed: 0 0 0 */ {
b0 -> a0;
b0 -> a1;
b0 -> a2;
b0 -> a3;
b1 -> a0;
b1 -> a1;
b1 -> a2;
b1 -> a3;
b2 -> a0;
b2 -> a1;
b2 -> a2;
b2 -> a3;
b3 -> a0;
b3 -> a1;
b3 -> a2;
b3 -> a3;
b4 -> a0;
b4 -> a1;
b4 -> a2;
b4 -> a3;
}