 Michael Buesch
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1dd232c089
Add generator test
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1 year ago |
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Michael Buesch
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64117d9547
Bump version
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1 year ago |
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Michael Buesch
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7e1173cb19
Keep local ref to P
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1 year ago |
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Michael Buesch
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91fafc4a55
Move test code to own file and don't import in normal runs
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1 year ago |
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Michael Buesch
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18c98d5f62
Argument cleanups
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1 year ago |
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Michael Buesch
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07414e97b3
Hide test mode
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1 year ago |
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Michael Buesch
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dde6791dac
Update release script
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1 year ago |
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Michael Buesch
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d86ef9f170
Use setuptools instead of distutils
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1 year ago |
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Michael Buesch
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e11d32169f
Readme: Update name spelling
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1 year ago |
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Michael Buesch
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d03234621a
Readme: Add HDL code license
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1 year ago |
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Michael Buesch
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13c1a79647
Update Readme
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1 year ago |
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Michael Buesch
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56986e2db4
Bump version
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2 years ago |
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Michael Buesch
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4f2a2f648c
Unify indentation among all supported languages
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2 years ago |
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Michael Buesch
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b420326d54
Don't generate trailing comma in Verilog module parameter list
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2 years ago |
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Michael Buesch
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c2f1431dea
Bump version
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2 years ago |
|
Michael Buesch
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7843ea9702
Add examples to Readme
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2 years ago |
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Michael Buesch
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804da5ded3
Fix release script
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2 years ago |
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Michael Buesch
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6af398eca5
setup: Update keywords
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2 years ago |
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Michael Buesch
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d4496951ff
Rename main module to libcrcgen
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2 years ago |
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Michael Buesch
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9d3f8b3013
Fix VHDL bits
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2 years ago |
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Michael Buesch
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a8109841b2
Print language in header
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2 years ago |
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Michael Buesch
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e48104e66d
Reorder options
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2 years ago |
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Michael Buesch
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628df645d7
Simplify generated Python code
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2 years ago |
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Michael Buesch
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754c08730e
generator: Add VHDL support
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2 years ago |
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Michael Buesch
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fced163590
generator: Frequently run the optimization.
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2 years ago |
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Michael Buesch
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f8d23140cf
Convert everything to f-strings
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2 years ago |
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Michael Buesch
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495634c26c
generator: Add MyHDL support
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2 years ago |
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Michael Buesch
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eaa5d091b7
Update release script
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2 years ago |
|
Michael Buesch
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af2cec8517
Bump version
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2 years ago |
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Michael Buesch
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10ddae1162
Add link to generated header
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2 years ago |
