prt33l17lcd.h 2.9 KB

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  1. #ifndef WIKIREADER_PRT33L17LCD_H
  2. #define WIKIREADER_PRT33L17LCD_H
  3. #define EEPROM_MP45PE80 1
  4. static inline void init_pins(void)
  5. {
  6. #if 0 // not enough space for adding this
  7. // A low on pin P63 shuts down the power supply - so try
  8. // to keep it high, without any glitched or we will power down
  9. // immediately.
  10. // This _must_ be the setting performed.
  11. // p60-63: wdt - ensure that P63(#WDTNMI) pin is set high
  12. REG_P6_P6D |= (1 << 3); // P63 = 1 (for safety)
  13. REG_P6_03_CFP &= 0x3f; // P63 = input
  14. REG_MISC_PUP6 |= (1 << 3); // P63 pullup = on
  15. #endif
  16. /* P85: LCD_CS, P83: TFT_CTL1 */
  17. REG_P8_IOC8 = 0x28;
  18. REG_P8_03_CFP = 0x3f;
  19. REG_P8_45_CFP = 0x03;
  20. /* P65-67: SPI */
  21. REG_P6_47_CFP = 0x54;
  22. /* Serial interface */
  23. REG_P0_03_CFP = 0x05;
  24. /* LCD controller */
  25. REG_P8_03_CFP = 0x15;
  26. REG_P9_47_CFP = 0x55;
  27. /* board specific things */
  28. /* SDCARD CS# */
  29. REG_P8_IOC8 = (1 << 3);
  30. /* EEPROM WP# */
  31. REG_P1_IOC1 = (1 << 4);
  32. /* P50 & P52: CS lines */
  33. REG_P5_IOC5 = 0x07;
  34. }
  35. /* MRS command address for burst length=1, CAS latency = 2 */
  36. #define MRSREG (*(volatile unsigned char *) 0x10000442)
  37. #define RAMDUMMY (*(volatile unsigned char *) 0x10000000)
  38. static inline void init_ram(void)
  39. {
  40. int i;
  41. /* P20-P27 functions */
  42. REG_P2_03_CFP = 0x55;
  43. REG_P2_47_CFP = 0x55;
  44. REG_P5_03_CFP |= 0x80;
  45. /* P85 */
  46. REG_P8_45_CFP &= 0x03;
  47. /* disable write protection of clock registers */
  48. REG_CMU_PROTECT = 0x96;
  49. /* switch on SDRAM clk */
  50. REG_CMU_GATEDCLK0 |= 0x78;
  51. /* re-enable write protection of clock registers */
  52. REG_CMU_PROTECT = 0x00;
  53. /* enable SDRAMC application core */
  54. REG_SDRAMC_APP = 0x8000000b;
  55. /* set up SDRAM controller */
  56. /* 4M x 16 bits x 1, 15 Trs/Trfc/Txsr cycles, 3 Tras, 2 Trp */
  57. //REG_SDRAMC_CTL = 0x37e1;
  58. REG_SDRAMC_CTL = 0x37e3;
  59. /* disable RAM self-refresh, ... */
  60. REG_SDRAMC_REF = 0x8c | (1 << 23) | (0x7f << 16);
  61. /* enter RAM setup mode */
  62. REG_SDRAMC_INI = 0x14;
  63. /* SDRAM command sequence: PALL - REF - REF - MRS (for MT48LC16M16A2) */
  64. REG_SDRAMC_INI = 0x12; /* INIPRE */
  65. RAMDUMMY = 0x0; /* dummy write */
  66. REG_SDRAMC_INI = 0x12; /* INIPRE */
  67. RAMDUMMY = 0x0; /* dummy write */
  68. for (i = 0; i < 2; i++) {
  69. REG_SDRAMC_INI = 0x11; /* INIREF */
  70. RAMDUMMY = 0x0; /* dummy write */
  71. }
  72. REG_SDRAMC_INI = 0x14; /* INIMRS */
  73. MRSREG = 0x0; /* dummy write */
  74. /* exit RAM setup mode */
  75. REG_SDRAMC_INI = 0x10;
  76. }
  77. static inline void enable_card_power(void)
  78. {
  79. REG_SRAMC_A0_BSL |= 1 << 1;
  80. *(volatile unsigned int *) 0x200000 = 0xffffffff;
  81. }
  82. static inline void disable_card_power(void)
  83. {
  84. REG_SRAMC_A0_BSL |= 1 << 1;
  85. *(volatile unsigned int *) 0x200000 = 0;
  86. }
  87. #define SDCARD_CS_LO() do { REG_P8_P8D &= ~(1 << 4); } while (0)
  88. #define SDCARD_CS_HI() do { REG_P8_P8D |= (1 << 4); } while (0)
  89. #define EEPROM_WP_HI() do { REG_P2_P2D = (1 << 6); } while (0)
  90. #define power_off() do {} while(0)
  91. #define prepare_keys() do {} while(0)
  92. #define get_key_state() 0
  93. #endif /* WIKIREADER_PRT33L17LCD_H */