 Benjamin Herrenschmidt
|
bf7def5503
soc: Don't require dram wishbones signals to be wired by toplevel
|
4 years ago |
|
Benjamin Herrenschmidt
|
1ffc89e58b
soc: Add defaults for some input signals
|
4 years ago |
|
Benjamin Herrenschmidt
|
4244b54984
soc: Remove unused RESET_LOW generic
|
4 years ago |
|
Benjamin Herrenschmidt
|
cc4dcb3597
spi: Add SPI Flash controller
|
4 years ago |
|
Benjamin Herrenschmidt
|
573b6b4bc4
soc: Rework interconnect
|
4 years ago |
|
Benjamin Herrenschmidt
|
025cf5efe8
syscon: Add syscon registers
|
5 years ago |
|
Benjamin Herrenschmidt
|
8bb3c8f8b6
soc: Add DRAM address decoding
|
5 years ago |
|
Benjamin Herrenschmidt
|
6853d22203
core: Add alternate reset address
|
4 years ago |
 Anton Blanchard
|
f5424f8e71
Reduce simulated and default FPGA RAM to 384kB
|
4 years ago |
|
Benjamin Herrenschmidt
|
8e0389b973
ram: Rework main RAM interface
|
5 years ago |
|
Benjamin Herrenschmidt
|
98f0994698
Add core debug module
|
5 years ago |
|
Anton Blanchard
|
89849a6856
Add a simple direct mapped icache
|
5 years ago |
|
Benjamin Herrenschmidt
|
3ac1dbc737
Share soc.vhdl between FPGA and sim
|
5 years ago |
|
Benjamin Herrenschmidt
|
c97b080d8c
Move wishbone arbiter out of the core
|
5 years ago |
|
Benjamin Herrenschmidt
|
8bfd6e5eae
Use simulated UART in core test bench
|
5 years ago |
|
Anton Blanchard
|
1fa0b332ca
micropython only requires 512kB of BRAM
|
5 years ago |
|
Anton Blanchard
|
5a29cb4699
Initial import of microwatt
|
5 years ago |
