.github
|
93b2987b19
ci: use job.container
|
3 years ago |
constraints
|
9a967e764b
found chiselwatt ulx3s constraint file
|
2 years ago |
fpga
|
72ae258962
inital support for orangecrab0.2
|
2 years ago |
hello_world
|
bc4e6b7efe
Reduce hello_world footprint to fit in 8kB
|
3 years ago |
include
|
9b5bd2d757
rrright. ok. these modifications to sdram_init allow it
|
2 years ago |
lib
|
d654667304
console: Add support for the 16550 UART
|
4 years ago |
litedram
|
d58b112a12
add EXTRA_CFLAGS to CFLAGS
|
2 years ago |
liteeth
|
8366710217
liteeth: Hook up LiteX LiteEth ethernet controller
|
4 years ago |
media
|
0cb0f78777
Add title image
|
5 years ago |
micropython
|
434962bc34
tests: Add updated micropython build with 16550 support
|
4 years ago |
openocd
|
d92624f9c0
add ulx3s openocd config for ft232
|
2 years ago |
rust_lib_demo
|
e3941109af
console: Cleanup console API
|
4 years ago |
scripts
|
89a67a18d0
decode: Add a facility field to the instruction decode tables
|
3 years ago |
sim-unisim
|
ee52fd4d80
Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
|
5 years ago |
tests
|
81b96e024e
add first cut of ulx3s constraint file
|
2 years ago |
uart16550
|
aae45583d7
Add uart16550 files from fusesoc
|
4 years ago |
verilator
|
81b96e024e
add first cut of ulx3s constraint file
|
2 years ago |
.gitignore
|
3460afb557
Add yosys builds files to gitignore
|
4 years ago |
LICENSE
|
5a29cb4699
Initial import of microwatt
|
5 years ago |
Makefile
|
72ae258962
inital support for orangecrab0.2
|
2 years ago |
README.md
|
6326efaca4
Add Makefile command line variables to enable docker and podman
|
4 years ago |
cache_ram.vhdl
|
ecaa5e2fb2
dcache: Rework RAM wrapper to synthetize better on Xilinx
|
4 years ago |
common.vhdl
|
f636bb7c39
dcache: Fix bugs in pipelined operation
|
3 years ago |
control.vhdl
|
3cd3449b4b
core: Move redirect and interrupt delivery logic to writeback
|
3 years ago |
core.vhdl
|
1610e1fa21
add verilator snoop of LDST request address
|
2 years ago |
core_debug.vhdl
|
3361c460b8
core_debug: Stop logging 256 cycles after trigger
|
3 years ago |
core_dram_tb.vhdl
|
02abb135a8
litedram: l2: Add support for more geometries
|
4 years ago |
core_dummy.vhdl
|
1610e1fa21
add verilator snoop of LDST request address
|
2 years ago |
core_flash_tb.vhdl
|
bf7def5503
soc: Don't require dram wishbones signals to be wired by toplevel
|
4 years ago |
core_tb.vhdl
|
bf7def5503
soc: Don't require dram wishbones signals to be wired by toplevel
|
4 years ago |
countzero.vhdl
|
9d285a265c
core: Add support for single-precision FP loads and stores
|
4 years ago |
countzero_tb.vhdl
|
ab86b58d95
Exit cleanly from testbench on success
|
4 years ago |
cr_file.vhdl
|
893d2bc6a2
core: Don't generate logic for log data when LOG_LENGTH = 0
|
4 years ago |
crhelpers.vhdl
|
da0bd89c43
crhelpers: Constraint "crnum" integer
|
4 years ago |
dcache.vhdl
|
f636bb7c39
dcache: Fix bugs in pipelined operation
|
3 years ago |
dcache_tb.vhdl
|
ab86b58d95
Exit cleanly from testbench on success
|
4 years ago |
decode1.vhdl
|
ae2afeca5c
core: Track CR hazards and bypasses using tags
|
3 years ago |
decode2.vhdl
|
4fd8d9509c
execute1: Move CR result to data path process
|
3 years ago |
decode_types.vhdl
|
4c61a71a62
core: Crack update-form loads into two internal ops
|
3 years ago |
divider.vhdl
|
c9a2076dd3
execute1: Remember dest GPR, RC, OE, XER for slow operations
|
4 years ago |
divider_tb.vhdl
|
ab86b58d95
Exit cleanly from testbench on success
|
4 years ago |
dmi_dtm_dummy.vhdl
|
8102e7863b
Fix build issue in dmi_dtm_dummy.vhdl
|
5 years ago |
dmi_dtm_ecp5.vhdl
|
72ae258962
inital support for orangecrab0.2
|
2 years ago |
dmi_dtm_tb.vhdl
|
8e0389b973
ram: Rework main RAM interface
|
4 years ago |
dmi_dtm_xilinx.vhdl
|
5eb351b4be
Reset JTAG/DMI
|
3 years ago |
dram_tb.vhdl
|
02abb135a8
litedram: l2: Add support for more geometries
|
4 years ago |
execute1.vhdl
|
acb3d2d745
core: Send FPU interrupts to writeback rather than execute1
|
3 years ago |
fetch1.vhdl
|
3cd3449b4b
core: Move redirect and interrupt delivery logic to writeback
|
3 years ago |
fpu.vhdl
|
acb3d2d745
core: Send FPU interrupts to writeback rather than execute1
|
3 years ago |
glibc_random.vhdl
|
06392e7eaa
Reformat glibc_random
|
5 years ago |
glibc_random_helpers.vhdl
|
06392e7eaa
Reformat glibc_random
|
5 years ago |
helpers.vhdl
|
9d285a265c
core: Add support for single-precision FP loads and stores
|
4 years ago |
icache.vhdl
|
0fb207be60
fetch1: Implement a simple branch target cache
|
3 years ago |
icache_tb.vhdl
|
b5a7dbb78d
core: Remove fetch2 pipeline stage
|
4 years ago |
icache_test.bin
|
f74e8a4f79
icache_tb: Improve test and include test file
|
4 years ago |
insn_helpers.vhdl
|
4b2c23703c
core: Implement quadword loads and stores
|
3 years ago |
loadstore1.vhdl
|
f636bb7c39
dcache: Fix bugs in pipelined operation
|
3 years ago |
logical.vhdl
|
658feabfd4
core: Make result multiplexing explicit
|
3 years ago |
microwatt.core
|
ae2afeca5c
core: Track CR hazards and bypasses using tags
|
3 years ago |
mmu.vhdl
|
740f013284
Initialize PID register
|
3 years ago |
multiply.vhdl
|
f1238299bd
execute1: Take an extra cycle for OE=1 multiply instructions
|
4 years ago |
multiply_tb.vhdl
|
535341961d
multiplier: Generalize interface to the multiplier
|
4 years ago |
nonrandom.vhdl
|
1a7aebeef8
Add random number generator and implement the darn instruction
|
4 years ago |
plru.vhdl
|
e598188aca
plru: Improve sensitivity list
|
4 years ago |
plru_tb.vhdl
|
ab86b58d95
Exit cleanly from testbench on success
|
4 years ago |
ppc_fx_insns.vhdl
|
8edfbf638b
core: Implement the cmpeqb and cmprb instructions
|
4 years ago |
random.vhdl
|
1a7aebeef8
Add random number generator and implement the darn instruction
|
4 years ago |
register_file.vhdl
|
45cd8f4fc3
core: Add support for floating-point loads and stores
|
4 years ago |
rotator.vhdl
|
8a0a907e2f
Implement the extswsli instruction
|
4 years ago |
rotator_tb.vhdl
|
ab86b58d95
Exit cleanly from testbench on success
|
4 years ago |
sim_16550_uart.vhdl
|
cc10f6b289
uart: Add a simulation model for the 16550 compatible UART
|
4 years ago |
sim_bram.vhdl
|
8e0389b973
ram: Rework main RAM interface
|
4 years ago |
sim_bram_helpers.vhdl
|
8e0389b973
ram: Rework main RAM interface
|
4 years ago |
sim_bram_helpers_c.c
|
471c7e2197
Consolidate VHPI code
|
4 years ago |
sim_console.vhdl
|
fd9e971b2c
Reformat sim_console
|
5 years ago |
sim_console_c.c
|
fc4e13ae67
sim_console: Fix polling to check for POLLIN
|
4 years ago |
sim_jtag.vhdl
|
554b753172
Add jtag support in simulation via a socket
|
5 years ago |
sim_jtag_socket.vhdl
|
554b753172
Add jtag support in simulation via a socket
|
5 years ago |
sim_jtag_socket_c.c
|
471c7e2197
Consolidate VHPI code
|
4 years ago |
sim_no_flash.vhdl
|
a89e1469ef
spi: Add simulation support
|
4 years ago |
sim_pp_uart.vhdl
|
4eae29801b
uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
|
4 years ago |
sim_vhpi_c.c
|
471c7e2197
Consolidate VHPI code
|
4 years ago |
sim_vhpi_c.h
|
471c7e2197
Consolidate VHPI code
|
4 years ago |
soc.vhdl
|
79461a96bd
link unused signals to undefined
|
2 years ago |
spi_flash_ctrl.vhdl
|
c870040a20
Fix an issue in flash controller when BOOT_CLOCKS is false
|
3 years ago |
spi_rxtx.vhdl
|
3f1e2b3a4f
Merge pull request #265 from antonblanchard/another-spi-rxtx-reset-issu
|
3 years ago |
sync_fifo.vhdl
|
a3857aac94
litedram: Add an L2 cache with store queue
|
4 years ago |
syscon.vhdl
|
6431824a5f
add SIM_BRAM_CHAINBOOT parameter to SYSCON
|
2 years ago |
utils.vhdl
|
bf1b98b958
litedram: Add support for booting without BRAM
|
4 years ago |
wishbone_arbiter.vhdl
|
cff4b13a9b
wb_arbiter: Early master selection
|
4 years ago |
wishbone_bram_tb.bin
|
8e0389b973
ram: Rework main RAM interface
|
4 years ago |
wishbone_bram_tb.vhdl
|
ab86b58d95
Exit cleanly from testbench on success
|
4 years ago |
wishbone_bram_wrapper.vhdl
|
2260ca654d
gotten over the logic-dyslexia of what in/out mean in VHDL.
|
2 years ago |
wishbone_debug_master.vhdl
|
fe789190e4
wishbone_debug_master: Fix address auto-increment for memory writes
|
4 years ago |
wishbone_types.vhdl
|
c6dfc19d89
Make wishbone_master_out and wb_io_master_out match
|
3 years ago |
writeback.vhdl
|
acb3d2d745
core: Send FPU interrupts to writeback rather than execute1
|
3 years ago |
xics.vhdl
|
bb54af59de
xics: Add support for reduced priority field size
|
4 years ago |
xilinx-mult.vhdl
|
f1238299bd
execute1: Take an extra cycle for OE=1 multiply instructions
|
4 years ago |