if_dc_cardbus.c 9.1 KB

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  1. /* $OpenBSD: if_dc_cardbus.c,v 1.38 2015/05/04 03:59:42 jsg Exp $ */
  2. /*
  3. * Copyright (c) 1997, 1998, 1999
  4. * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright
  12. * notice, this list of conditions and the following disclaimer in the
  13. * documentation and/or other materials provided with the distribution.
  14. * 3. All advertising materials mentioning features or use of this software
  15. * must display the following acknowledgement:
  16. * This product includes software developed by Bill Paul.
  17. * 4. Neither the name of the author nor the names of any co-contributors
  18. * may be used to endorse or promote products derived from this software
  19. * without specific prior written permission.
  20. *
  21. * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24. * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31. * THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. * $FreeBSD: src/sys/pci/if_dc.c,v 1.5 2000/01/12 22:24:05 wpaul Exp $
  34. */
  35. #include <sys/param.h>
  36. #include <sys/systm.h>
  37. #include <sys/mbuf.h>
  38. #include <sys/socket.h>
  39. #include <sys/ioctl.h>
  40. #include <sys/errno.h>
  41. #include <sys/malloc.h>
  42. #include <sys/kernel.h>
  43. #include <sys/device.h>
  44. #include <net/if.h>
  45. #include <net/if_dl.h>
  46. #include <net/if_types.h>
  47. #include <net/if_media.h>
  48. #include <netinet/in.h>
  49. #include <netinet/if_ether.h>
  50. #include <dev/mii/miivar.h>
  51. #include <machine/bus.h>
  52. #include <dev/pci/pcivar.h>
  53. #include <dev/pci/pcireg.h>
  54. #include <dev/pci/pcidevs.h>
  55. #include <dev/cardbus/cardbusvar.h>
  56. #include <dev/ic/dcreg.h>
  57. /* PCI configuration regs */
  58. #define PCI_CBIO 0x10
  59. #define PCI_CBMEM 0x14
  60. #define PCI_CFDA 0x40
  61. #define DC_CFDA_SUSPEND 0x80000000
  62. #define DC_CFDA_STANDBY 0x40000000
  63. struct dc_cardbus_softc {
  64. struct dc_softc sc_dc;
  65. int sc_intrline;
  66. cardbus_devfunc_t sc_ct;
  67. pci_chipset_tag_t sc_pc;
  68. pcitag_t sc_tag;
  69. bus_size_t sc_mapsize;
  70. int sc_actype;
  71. };
  72. int dc_cardbus_match(struct device *, void *, void *);
  73. void dc_cardbus_attach(struct device *, struct device *,void *);
  74. int dc_cardbus_detach(struct device *, int);
  75. void dc_cardbus_setup(struct dc_cardbus_softc *csc);
  76. struct cfattach dc_cardbus_ca = {
  77. sizeof(struct dc_cardbus_softc), dc_cardbus_match, dc_cardbus_attach,
  78. dc_cardbus_detach, dc_activate
  79. };
  80. const struct pci_matchid dc_cardbus_devices[] = {
  81. { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21142 },
  82. { PCI_VENDOR_XIRCOM, PCI_PRODUCT_XIRCOM_X3201_3_21143 },
  83. { PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_AN985 },
  84. { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_EN2242 },
  85. { PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2500 },
  86. { PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2500MX },
  87. { PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_PCM200 },
  88. { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DRP32TXD },
  89. { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_PCMPC200 },
  90. { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_PCM200 },
  91. { PCI_VENDOR_HAWKING, PCI_PRODUCT_HAWKING_PN672TX },
  92. { PCI_VENDOR_MICROSOFT, PCI_PRODUCT_MICROSOFT_MN120 },
  93. };
  94. int
  95. dc_cardbus_match(struct device *parent, void *match, void *aux)
  96. {
  97. return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
  98. dc_cardbus_devices, nitems(dc_cardbus_devices)));
  99. }
  100. void
  101. dc_cardbus_attach(struct device *parent, struct device *self, void *aux)
  102. {
  103. struct dc_cardbus_softc *csc = (struct dc_cardbus_softc *)self;
  104. struct dc_softc *sc = &csc->sc_dc;
  105. struct cardbus_attach_args *ca = aux;
  106. struct cardbus_devfunc *ct = ca->ca_ct;
  107. cardbus_chipset_tag_t cc = ct->ct_cc;
  108. pci_chipset_tag_t pc = ca->ca_pc;
  109. cardbus_function_tag_t cf = ct->ct_cf;
  110. pcireg_t reg;
  111. bus_addr_t addr;
  112. sc->sc_dmat = ca->ca_dmat;
  113. csc->sc_ct = ct;
  114. csc->sc_tag = ca->ca_tag;
  115. csc->sc_pc = ca->ca_pc;
  116. Cardbus_function_enable(ct);
  117. if (Cardbus_mapreg_map(ct, PCI_CBIO,
  118. PCI_MAPREG_TYPE_IO, 0, &sc->dc_btag, &sc->dc_bhandle, &addr,
  119. &csc->sc_mapsize) == 0) {
  120. csc->sc_actype = CARDBUS_IO_ENABLE;
  121. } else if (Cardbus_mapreg_map(ct, PCI_CBMEM,
  122. PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
  123. &sc->dc_btag, &sc->dc_bhandle, &addr, &csc->sc_mapsize) == 0) {
  124. csc->sc_actype = CARDBUS_MEM_ENABLE;
  125. } else {
  126. printf(": can't map device registers\n");
  127. return;
  128. }
  129. csc->sc_intrline = ca->ca_intrline;
  130. sc->dc_cachesize = pci_conf_read(csc->sc_pc, ca->ca_tag, DC_PCI_CFLT)
  131. & 0xFF;
  132. dc_cardbus_setup(csc);
  133. /* Get the eeprom width */
  134. if ((PCI_VENDOR(ca->ca_id) == PCI_VENDOR_XIRCOM &&
  135. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_XIRCOM_X3201_3_21143))
  136. ; /* XIRCOM has non-standard eeprom */
  137. else
  138. dc_eeprom_width(sc);
  139. switch (PCI_VENDOR(ca->ca_id)) {
  140. case PCI_VENDOR_DEC:
  141. if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21142) {
  142. sc->dc_type = DC_TYPE_21143;
  143. sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
  144. sc->dc_flags |= DC_REDUCED_MII_POLL;
  145. dc_read_srom(sc, sc->dc_romwidth);
  146. dc_parse_21143_srom(sc);
  147. }
  148. break;
  149. case PCI_VENDOR_XIRCOM:
  150. if (PCI_PRODUCT(ca->ca_id) ==
  151. PCI_PRODUCT_XIRCOM_X3201_3_21143) {
  152. sc->dc_type = DC_TYPE_XIRCOM;
  153. sc->dc_flags |= DC_TX_INTR_ALWAYS|DC_TX_COALESCE |
  154. DC_TX_ALIGN;
  155. sc->dc_pmode = DC_PMODE_MII;
  156. }
  157. break;
  158. case PCI_VENDOR_ADMTEK:
  159. case PCI_VENDOR_ACCTON:
  160. case PCI_VENDOR_ABOCOM:
  161. case PCI_VENDOR_DLINK:
  162. case PCI_VENDOR_LINKSYS:
  163. case PCI_VENDOR_HAWKING:
  164. case PCI_VENDOR_MICROSOFT:
  165. if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ADMTEK_AN985 ||
  166. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ACCTON_EN2242 ||
  167. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500 ||
  168. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500MX ||
  169. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_PCM200 ||
  170. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DLINK_DRP32TXD ||
  171. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCMPC200 ||
  172. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCM200 ||
  173. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_HAWKING_PN672TX ||
  174. PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_MICROSOFT_MN120) {
  175. sc->dc_type = DC_TYPE_AN983;
  176. sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_ADMTEK_WAR |
  177. DC_64BIT_HASH;
  178. sc->dc_pmode = DC_PMODE_MII;
  179. /* Don't read SROM for - auto-loaded on reset */
  180. }
  181. break;
  182. default:
  183. printf(": unknown device\n");
  184. return;
  185. }
  186. /*
  187. * set latency timer, do we really need this?
  188. */
  189. reg = pci_conf_read(pc, ca->ca_tag, PCI_BHLC_REG);
  190. if (PCI_LATTIMER(reg) < 0x20) {
  191. reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
  192. reg |= (0x20 << PCI_LATTIMER_SHIFT);
  193. pci_conf_write(pc, ca->ca_tag, PCI_BHLC_REG, reg);
  194. }
  195. sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_NET,
  196. dc_intr, csc, sc->sc_dev.dv_xname);
  197. if (sc->sc_ih == NULL) {
  198. printf(": can't establish interrupt at %d\n",
  199. ca->ca_intrline);
  200. return;
  201. }
  202. printf(": irq %d", ca->ca_intrline);
  203. dc_reset(sc);
  204. sc->dc_revision = PCI_REVISION(ca->ca_class);
  205. dc_attach(sc);
  206. }
  207. int
  208. dc_cardbus_detach(struct device *self, int flags)
  209. {
  210. struct dc_cardbus_softc *csc = (struct dc_cardbus_softc *)self;
  211. struct dc_softc *sc = &csc->sc_dc;
  212. struct cardbus_devfunc *ct = csc->sc_ct;
  213. cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
  214. dc_detach(sc);
  215. /* unmap cardbus resources */
  216. Cardbus_mapreg_unmap(ct,
  217. csc->sc_actype == CARDBUS_IO_ENABLE ? PCI_CBIO : PCI_CBMEM,
  218. sc->dc_btag, sc->dc_bhandle, csc->sc_mapsize);
  219. return (0);
  220. }
  221. void
  222. dc_cardbus_setup(struct dc_cardbus_softc *csc)
  223. {
  224. cardbus_devfunc_t ct = csc->sc_ct;
  225. cardbus_chipset_tag_t cc = ct->ct_cc;
  226. pci_chipset_tag_t pc = csc->sc_pc;
  227. pcireg_t reg;
  228. int r;
  229. /* wakeup the card if needed */
  230. reg = pci_conf_read(pc, csc->sc_tag, PCI_CFDA);
  231. if (reg & (DC_CFDA_SUSPEND|DC_CFDA_STANDBY)) {
  232. pci_conf_write(pc, csc->sc_tag, PCI_CFDA,
  233. reg & ~(DC_CFDA_SUSPEND|DC_CFDA_STANDBY));
  234. }
  235. if (pci_get_capability(csc->sc_pc, csc->sc_tag, PCI_CAP_PWRMGMT, &r,
  236. 0)) {
  237. r = pci_conf_read(csc->sc_pc, csc->sc_tag, r + 4) & 3;
  238. if (r) {
  239. printf("%s: awakening from state D%d\n",
  240. csc->sc_dc.sc_dev.dv_xname, r);
  241. pci_conf_write(csc->sc_pc, csc->sc_tag, r + 4, 0);
  242. }
  243. }
  244. (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_actype);
  245. (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
  246. reg = pci_conf_read(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
  247. reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
  248. PCI_COMMAND_MASTER_ENABLE;
  249. pci_conf_write(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
  250. reg = pci_conf_read(csc->sc_pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
  251. }