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- # HOW TO EDIT THIS FILE:
- # The "handy ruler" below makes it easier to edit a package description.
- # Line up the first '|' above the ':' following the base package name, and
- # the '|' on the right side marks the last column you can put a character in.
- # You must make exactly 11 lines for the formatting to be correct. It's also
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- |-----handy-ruler------------------------------------------------------|
- verilator: verilator (the fastest free Verilog HDL simulator)
- verilator:
- verilator: Verilator is invoked with parameters similar to GCC or Synopsys's
- verilator: VCS. It "Verilates" the specified synthesizable Verilog or
- verilator: SystemVerilog code by reading it, performing lint checks, and
- verilator: optionally inserting assertion checks and coverage-analysis points.
- verilator: It outputs single- or verilator: multi-threaded .cpp and .h files,
- verilator: the "Verilated" code.
- verilator:
- verilator: homepage: https://www.veripool.org/wiki/verilator
- verilator:
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