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  1. # HOW TO EDIT THIS FILE:
  2. # The "handy ruler" below makes it easier to edit a package description.
  3. # Line up the first '|' above the ':' following the base package name, and
  4. # the '|' on the right side marks the last column you can put a character in.
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  7. |-----handy-ruler------------------------------------------------------|
  8. verilator: verilator (the fastest free Verilog HDL simulator)
  9. verilator:
  10. verilator: Verilator is invoked with parameters similar to GCC or Synopsys's
  11. verilator: VCS. It "Verilates" the specified synthesizable Verilog or
  12. verilator: SystemVerilog code by reading it, performing lint checks, and
  13. verilator: optionally inserting assertion checks and coverage-analysis points.
  14. verilator: It outputs single- or verilator: multi-threaded .cpp and .h files,
  15. verilator: the "Verilated" code.
  16. verilator:
  17. verilator: homepage: https://www.veripool.org/wiki/verilator
  18. verilator: