dsomero d0c108251a various: Update find command to match template. 11 年之前
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README da95dc10a4 academic/verilog: Added to 13.0 repository 14 年之前
slack-desc 610e8461bb various: Fix slack-desc formatting and comment nit picks. 11 年之前
verilog.SlackBuild d0c108251a various: Update find command to match template. 11 年之前
verilog.info 6731e7a316 academic/verilog: Updated for version 0.9.7. 11 年之前

README

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an intermediate
form called vvp assembly. This intermediate form is executed by the 'vvp'
command. For synthesis, the compiler generates netlists in the desired format.