Puu:
67dec11b58
11.0
12.0
12.1
12.2
13.0
13.1
13.37
14.0
14.1
14.2
15.0
bedlam
bedlam-name-fixes
dive
erik
gitignore
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master
misc-fixes
python-renames
rworkman
urchlay
user/aclemons/updates
user/anddt/development/acpica
user/anddt/development/glm
user/anddt/development/gnustep-base
user/anddt/development/gnustep-make
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user/anddt/games/prboom-plus
user/anddt/games/rocksndiamonds
user/anddt/games/rottexpr
user/anddt/games/srb2
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user/anddt/ham/chirp
user/anddt/ham/hamlib
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user/anddt/libraries/libopenmpt
user/anddt/libraries/libtorrent
user/anddt/libraries/wxGTK3
user/anddt/libraries/xmlrpc-c
user/anddt/misc/discount
user/anddt/misc/slop
user/anddt/network/nethogs
user/anddt/network/putty
user/anddt/network/rclone
user/anddt/network/rtorrent
user/anddt/network/sshguard
user/anddt/network/strongswan
user/anddt/network/umurmur
user/anddt/network/yt-dlp
user/anddt/network/znc
user/anddt/office/gnumeric
user/anddt/office/sigil
user/anddt/system/FontAwesome
user/anddt/system/conky
user/anddt/system/fakeroot
user/anddt/system/hplip-plugin
user/anddt/system/postgresql
user/anddt/system/testdisk
user/anddt/system/worker
user/anddt/system/xen
user/anddt/system/zzzfm
user/belka/updates
user/chris.willing/updates
user/dslackw/updates
user/elyk/updates
user/kingbeowulf/updates
user/mario/updates
user/ponce/updates
user/pprkut/updates
willysr
wxWidgets-wip
GPG-KEY
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various: Update find command to match template.
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| README | da95dc10a4 academic/verilog: Added to 13.0 repository | 14 vuotta sitten |
| slack-desc | 610e8461bb various: Fix slack-desc formatting and comment nit picks. | 11 vuotta sitten |
| verilog.SlackBuild | d0c108251a various: Update find command to match template. | 11 vuotta sitten |
| verilog.info | 6731e7a316 academic/verilog: Updated for version 0.9.7. | 11 vuotta sitten |
README
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an intermediate
form called vvp assembly. This intermediate form is executed by the 'vvp'
command. For synthesis, the compiler generates netlists in the desired format.
a compiler, compiling source code written in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an intermediate
form called vvp assembly. This intermediate form is executed by the 'vvp'
command. For synthesis, the compiler generates netlists in the desired format.