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331a473f1a
11.0
12.0
12.1
12.2
13.0
13.1
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14.0
14.1
14.2
15.0
bedlam
bedlam-name-fixes
dive
erik
gitignore
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misc-fixes
python-renames
rworkman
urchlay
user/aclemons/updates
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user/anddt/development/glm
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user/anddt/network/umurmur
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user/anddt/office/gnumeric
user/anddt/office/sigil
user/anddt/system/FontAwesome
user/anddt/system/conky
user/anddt/system/fakeroot
user/anddt/system/hplip-plugin
user/anddt/system/postgresql
user/anddt/system/testdisk
user/anddt/system/worker
user/anddt/system/xen
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user/chris.willing/updates
user/dslackw/updates
user/elyk/updates
user/kingbeowulf/updates
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user/ponce/updates
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willysr
wxWidgets-wip
GPG-KEY
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Willy Sudiarto Raharjo
48fbd653f5
academic/verilog: Fix download url.
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| README | 9a5f389f29 academic/verilog: Fix README. | 4 lat temu |
| slack-desc | 610e8461bb various: Fix slack-desc formatting and comment nit picks. | 11 lat temu |
| verilog.SlackBuild | b66b94d5ec academic/verilog: Updated for version 11.0. | 2 lat temu |
| verilog.info | 48fbd653f5 academic/verilog: Fix download url. | 2 lat temu |
README
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can
generate an intermediate form called vvp assembly. This intermediate
form is executed by the 'vvp' command. For synthesis, the compiler
generates netlists in the desired format.
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can
generate an intermediate form called vvp assembly. This intermediate
form is executed by the 'vvp' command. For synthesis, the compiler
generates netlists in the desired format.