Tree:
0239b1e919
11.0
12.0
12.1
12.2
13.0
13.1
13.37
14.0
14.1
14.2
15.0
bedlam
bedlam-name-fixes
dive
erik
gitignore
libressl-gopher-test
master
misc-fixes
python-renames
rworkman
urchlay
user/aclemons/updates
user/anddt/development/acpica
user/anddt/development/glm
user/anddt/development/gnustep-base
user/anddt/development/gnustep-make
user/anddt/games/assaultcube-reloaded
user/anddt/games/doomseeker
user/anddt/games/prboom-plus
user/anddt/games/rocksndiamonds
user/anddt/games/rottexpr
user/anddt/games/srb2
user/anddt/graphics/blender
user/anddt/graphics/maim
user/anddt/ham/chirp
user/anddt/ham/hamlib
user/anddt/libraries/girara
user/anddt/libraries/goffice
user/anddt/libraries/gtksourceview4
user/anddt/libraries/imlib2
user/anddt/libraries/jsoncpp
user/anddt/libraries/libnova
user/anddt/libraries/libopenmpt
user/anddt/libraries/libtorrent
user/anddt/libraries/wxGTK3
user/anddt/libraries/xmlrpc-c
user/anddt/misc/discount
user/anddt/misc/slop
user/anddt/network/nethogs
user/anddt/network/putty
user/anddt/network/rclone
user/anddt/network/rtorrent
user/anddt/network/sshguard
user/anddt/network/strongswan
user/anddt/network/umurmur
user/anddt/network/yt-dlp
user/anddt/network/znc
user/anddt/office/gnumeric
user/anddt/office/sigil
user/anddt/system/FontAwesome
user/anddt/system/conky
user/anddt/system/fakeroot
user/anddt/system/hplip-plugin
user/anddt/system/postgresql
user/anddt/system/testdisk
user/anddt/system/worker
user/anddt/system/xen
user/anddt/system/zzzfm
user/belka/updates
user/chris.willing/updates
user/dslackw/updates
user/elyk/updates
user/kingbeowulf/updates
user/mario/updates
user/ponce/updates
user/pprkut/updates
willysr
wxWidgets-wip
GPG-KEY
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14.2-20210417.1
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14.2-20200112.1
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14.2-20191207.1
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Andrew Clemons
ef8e6a516c
academic/SimEng: Fix github tarball handling.
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2 years ago | |
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| README | e40642159b academic/SimEng: Added (cycle-accurate processor simulator) | 2 years ago |
| SimEng.SlackBuild | ef8e6a516c academic/SimEng: Fix github tarball handling. | 2 years ago |
| SimEng.info | ef8e6a516c academic/SimEng: Fix github tarball handling. | 2 years ago |
| slack-desc | e40642159b academic/SimEng: Added (cycle-accurate processor simulator) | 2 years ago |
README
SimEng is a framework for building modern, cycle-accurate processor
simulators. Its goals are to be:
- Fast, typically 4-5X faster than gem5
- Easy to use and modify to model desired microarchitecture
configurations. New cores can be configured in just a few hours
- Scalable, from simple scalar microarchitectures up to the most
sophisticated, superscalar, out-of-order designs
- Capable of supporting a wide range of instruction set
architectures (ISAs), starting with Armv8 but eventually including
RISC-V, x86, POWER, etc.
- Accurate, aiming for simulated cycle times being within 5-10% of
real hardware
- Open source, with a permissive license to enable collaboration
across academia and industry
SimEng places an emphasis on performance and ease of use, whilst
maintaining a clean, modern, simple and well-documented code base.
For example, the current out-of-order (OoO) model is implemented
in around 10,000 lines of simple C++, with another 9,000 lines or
so implementing the specifics of the Armv8 ISA, and around 13,000
lines of code in the accompanying test suite. SimEng should be
simple to read and understand, making it ideal to modify to your
requirements and include it in your projects.
Invocation example:
# simeng /usr/share/SimEng-0.9.4/configs/a64fx.yaml
simulators. Its goals are to be:
- Fast, typically 4-5X faster than gem5
- Easy to use and modify to model desired microarchitecture
configurations. New cores can be configured in just a few hours
- Scalable, from simple scalar microarchitectures up to the most
sophisticated, superscalar, out-of-order designs
- Capable of supporting a wide range of instruction set
architectures (ISAs), starting with Armv8 but eventually including
RISC-V, x86, POWER, etc.
- Accurate, aiming for simulated cycle times being within 5-10% of
real hardware
- Open source, with a permissive license to enable collaboration
across academia and industry
SimEng places an emphasis on performance and ease of use, whilst
maintaining a clean, modern, simple and well-documented code base.
For example, the current out-of-order (OoO) model is implemented
in around 10,000 lines of simple C++, with another 9,000 lines or
so implementing the specifics of the Armv8 ISA, and around 13,000
lines of code in the accompanying test suite. SimEng should be
simple to read and understand, making it ideal to modify to your
requirements and include it in your projects.
Invocation example:
# simeng /usr/share/SimEng-0.9.4/configs/a64fx.yaml