Ağaç:
0239b1e919
11.0
12.0
12.1
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14.0
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15.0
bedlam
bedlam-name-fixes
dive
erik
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urchlay
user/aclemons/updates
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user/anddt/development/gnustep-base
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user/anddt/network/sshguard
user/anddt/network/strongswan
user/anddt/network/umurmur
user/anddt/network/yt-dlp
user/anddt/network/znc
user/anddt/office/gnumeric
user/anddt/office/sigil
user/anddt/system/FontAwesome
user/anddt/system/conky
user/anddt/system/fakeroot
user/anddt/system/hplip-plugin
user/anddt/system/postgresql
user/anddt/system/testdisk
user/anddt/system/worker
user/anddt/system/xen
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user/chris.willing/updates
user/dslackw/updates
user/elyk/updates
user/kingbeowulf/updates
user/mario/updates
user/ponce/updates
user/pprkut/updates
willysr
wxWidgets-wip
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William PC
9e2c15d7ba
academic/DRAMSim2: Added (A cycle accurate DRAM simulator)
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2 yıl önce | |
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| .. | ||
| DRAMSim2.SlackBuild | 9e2c15d7ba academic/DRAMSim2: Added (A cycle accurate DRAM simulator) | 2 yıl önce |
| DRAMSim2.info | 9e2c15d7ba academic/DRAMSim2: Added (A cycle accurate DRAM simulator) | 2 yıl önce |
| README | 9e2c15d7ba academic/DRAMSim2: Added (A cycle accurate DRAM simulator) | 2 yıl önce |
| slack-desc | 9e2c15d7ba academic/DRAMSim2: Added (A cycle accurate DRAM simulator) | 2 yıl önce |
README
DRAMSim2 is a cycle accurate model of a DRAM memory controller, the
DRAM modules which comprise system storage, and the bus by which they
communicate. All major components in a modern memory system are
modeled as their own respective objects within the source, including:
ranks, banks, command queue, the memory controller, etc.
For setting the DEBUG mode use the enviroment variable DEBUG=1
DRAM modules which comprise system storage, and the bus by which they
communicate. All major components in a modern memory system are
modeled as their own respective objects within the source, including:
ranks, banks, command queue, the memory controller, etc.
For setting the DEBUG mode use the enviroment variable DEBUG=1