bf5xx-sport.c 27 KB

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  1. /*
  2. * File: bf5xx_sport.c
  3. * Based on:
  4. * Author: Roy Huang <roy.huang@analog.com>
  5. *
  6. * Created: Tue Sep 21 10:52:42 CEST 2004
  7. * Description:
  8. * Blackfin SPORT Driver
  9. *
  10. * Copyright 2004-2007 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/gpio.h>
  34. #include <linux/bug.h>
  35. #include <asm/portmux.h>
  36. #include <asm/dma.h>
  37. #include <asm/blackfin.h>
  38. #include <asm/cacheflush.h>
  39. #include "bf5xx-sport.h"
  40. /* delay between frame sync pulse and first data bit in multichannel mode */
  41. #define FRAME_DELAY (1<<12)
  42. /* note: multichannel is in units of 8 channels,
  43. * tdm_count is # channels NOT / 8 ! */
  44. int sport_set_multichannel(struct sport_device *sport,
  45. int tdm_count, u32 mask, int packed)
  46. {
  47. pr_debug("%s tdm_count=%d mask:0x%08x packed=%d\n", __func__,
  48. tdm_count, mask, packed);
  49. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  50. return -EBUSY;
  51. if (tdm_count & 0x7)
  52. return -EINVAL;
  53. if (tdm_count > 32)
  54. return -EINVAL; /* Only support less than 32 channels now */
  55. if (tdm_count) {
  56. sport->regs->mcmc1 = ((tdm_count>>3)-1) << 12;
  57. sport->regs->mcmc2 = FRAME_DELAY | MCMEN | \
  58. (packed ? (MCDTXPE|MCDRXPE) : 0);
  59. sport->regs->mtcs0 = mask;
  60. sport->regs->mrcs0 = mask;
  61. sport->regs->mtcs1 = 0;
  62. sport->regs->mrcs1 = 0;
  63. sport->regs->mtcs2 = 0;
  64. sport->regs->mrcs2 = 0;
  65. sport->regs->mtcs3 = 0;
  66. sport->regs->mrcs3 = 0;
  67. } else {
  68. sport->regs->mcmc1 = 0;
  69. sport->regs->mcmc2 = 0;
  70. sport->regs->mtcs0 = 0;
  71. sport->regs->mrcs0 = 0;
  72. }
  73. sport->regs->mtcs1 = 0; sport->regs->mtcs2 = 0; sport->regs->mtcs3 = 0;
  74. sport->regs->mrcs1 = 0; sport->regs->mrcs2 = 0; sport->regs->mrcs3 = 0;
  75. SSYNC();
  76. return 0;
  77. }
  78. EXPORT_SYMBOL(sport_set_multichannel);
  79. int sport_config_rx(struct sport_device *sport, unsigned int rcr1,
  80. unsigned int rcr2, unsigned int clkdiv, unsigned int fsdiv)
  81. {
  82. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  83. return -EBUSY;
  84. sport->regs->rcr1 = rcr1;
  85. sport->regs->rcr2 = rcr2;
  86. sport->regs->rclkdiv = clkdiv;
  87. sport->regs->rfsdiv = fsdiv;
  88. SSYNC();
  89. return 0;
  90. }
  91. EXPORT_SYMBOL(sport_config_rx);
  92. int sport_config_tx(struct sport_device *sport, unsigned int tcr1,
  93. unsigned int tcr2, unsigned int clkdiv, unsigned int fsdiv)
  94. {
  95. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  96. return -EBUSY;
  97. sport->regs->tcr1 = tcr1;
  98. sport->regs->tcr2 = tcr2;
  99. sport->regs->tclkdiv = clkdiv;
  100. sport->regs->tfsdiv = fsdiv;
  101. SSYNC();
  102. return 0;
  103. }
  104. EXPORT_SYMBOL(sport_config_tx);
  105. static void setup_desc(struct dmasg *desc, void *buf, int fragcount,
  106. size_t fragsize, unsigned int cfg,
  107. unsigned int x_count, unsigned int ycount, size_t wdsize)
  108. {
  109. int i;
  110. for (i = 0; i < fragcount; ++i) {
  111. desc[i].next_desc_addr = &(desc[i + 1]);
  112. desc[i].start_addr = (unsigned long)buf + i*fragsize;
  113. desc[i].cfg = cfg;
  114. desc[i].x_count = x_count;
  115. desc[i].x_modify = wdsize;
  116. desc[i].y_count = ycount;
  117. desc[i].y_modify = wdsize;
  118. }
  119. /* make circular */
  120. desc[fragcount-1].next_desc_addr = desc;
  121. pr_debug("setup desc: desc0=%p, next0=%p, desc1=%p,"
  122. "next1=%p\nx_count=%x,y_count=%x,addr=0x%lx,cfs=0x%x\n",
  123. desc, desc[0].next_desc_addr,
  124. desc+1, desc[1].next_desc_addr,
  125. desc[0].x_count, desc[0].y_count,
  126. desc[0].start_addr, desc[0].cfg);
  127. }
  128. static int sport_start(struct sport_device *sport)
  129. {
  130. enable_dma(sport->dma_rx_chan);
  131. enable_dma(sport->dma_tx_chan);
  132. sport->regs->rcr1 |= RSPEN;
  133. sport->regs->tcr1 |= TSPEN;
  134. SSYNC();
  135. return 0;
  136. }
  137. static int sport_stop(struct sport_device *sport)
  138. {
  139. sport->regs->tcr1 &= ~TSPEN;
  140. sport->regs->rcr1 &= ~RSPEN;
  141. SSYNC();
  142. disable_dma(sport->dma_rx_chan);
  143. disable_dma(sport->dma_tx_chan);
  144. return 0;
  145. }
  146. static inline int sport_hook_rx_dummy(struct sport_device *sport)
  147. {
  148. struct dmasg *desc, temp_desc;
  149. unsigned long flags;
  150. BUG_ON(sport->dummy_rx_desc == NULL);
  151. BUG_ON(sport->curr_rx_desc == sport->dummy_rx_desc);
  152. /* Maybe the dummy buffer descriptor ring is damaged */
  153. sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc + 1;
  154. local_irq_save(flags);
  155. desc = get_dma_next_desc_ptr(sport->dma_rx_chan);
  156. /* Copy the descriptor which will be damaged to backup */
  157. temp_desc = *desc;
  158. desc->x_count = sport->dummy_count / 2;
  159. desc->y_count = 0;
  160. desc->next_desc_addr = sport->dummy_rx_desc;
  161. local_irq_restore(flags);
  162. /* Waiting for dummy buffer descriptor is already hooked*/
  163. while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
  164. sizeof(struct dmasg)) != sport->dummy_rx_desc)
  165. continue;
  166. sport->curr_rx_desc = sport->dummy_rx_desc;
  167. /* Restore the damaged descriptor */
  168. *desc = temp_desc;
  169. return 0;
  170. }
  171. static inline int sport_rx_dma_start(struct sport_device *sport, int dummy)
  172. {
  173. if (dummy) {
  174. sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc;
  175. sport->curr_rx_desc = sport->dummy_rx_desc;
  176. } else
  177. sport->curr_rx_desc = sport->dma_rx_desc;
  178. set_dma_next_desc_addr(sport->dma_rx_chan, sport->curr_rx_desc);
  179. set_dma_x_count(sport->dma_rx_chan, 0);
  180. set_dma_x_modify(sport->dma_rx_chan, 0);
  181. set_dma_config(sport->dma_rx_chan, (DMAFLOW_LARGE | NDSIZE_9 | \
  182. WDSIZE_32 | WNR));
  183. set_dma_curr_addr(sport->dma_rx_chan, sport->curr_rx_desc->start_addr);
  184. SSYNC();
  185. return 0;
  186. }
  187. static inline int sport_tx_dma_start(struct sport_device *sport, int dummy)
  188. {
  189. if (dummy) {
  190. sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc;
  191. sport->curr_tx_desc = sport->dummy_tx_desc;
  192. } else
  193. sport->curr_tx_desc = sport->dma_tx_desc;
  194. set_dma_next_desc_addr(sport->dma_tx_chan, sport->curr_tx_desc);
  195. set_dma_x_count(sport->dma_tx_chan, 0);
  196. set_dma_x_modify(sport->dma_tx_chan, 0);
  197. set_dma_config(sport->dma_tx_chan,
  198. (DMAFLOW_LARGE | NDSIZE_9 | WDSIZE_32));
  199. set_dma_curr_addr(sport->dma_tx_chan, sport->curr_tx_desc->start_addr);
  200. SSYNC();
  201. return 0;
  202. }
  203. int sport_rx_start(struct sport_device *sport)
  204. {
  205. unsigned long flags;
  206. pr_debug("%s enter\n", __func__);
  207. if (sport->rx_run)
  208. return -EBUSY;
  209. if (sport->tx_run) {
  210. /* tx is running, rx is not running */
  211. BUG_ON(sport->dma_rx_desc == NULL);
  212. BUG_ON(sport->curr_rx_desc != sport->dummy_rx_desc);
  213. local_irq_save(flags);
  214. while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
  215. sizeof(struct dmasg)) != sport->dummy_rx_desc)
  216. continue;
  217. sport->dummy_rx_desc->next_desc_addr = sport->dma_rx_desc;
  218. local_irq_restore(flags);
  219. sport->curr_rx_desc = sport->dma_rx_desc;
  220. } else {
  221. sport_tx_dma_start(sport, 1);
  222. sport_rx_dma_start(sport, 0);
  223. sport_start(sport);
  224. }
  225. sport->rx_run = 1;
  226. return 0;
  227. }
  228. EXPORT_SYMBOL(sport_rx_start);
  229. int sport_rx_stop(struct sport_device *sport)
  230. {
  231. pr_debug("%s enter\n", __func__);
  232. if (!sport->rx_run)
  233. return 0;
  234. if (sport->tx_run) {
  235. /* TX dma is still running, hook the dummy buffer */
  236. sport_hook_rx_dummy(sport);
  237. } else {
  238. /* Both rx and tx dma will be stopped */
  239. sport_stop(sport);
  240. sport->curr_rx_desc = NULL;
  241. sport->curr_tx_desc = NULL;
  242. }
  243. sport->rx_run = 0;
  244. return 0;
  245. }
  246. EXPORT_SYMBOL(sport_rx_stop);
  247. static inline int sport_hook_tx_dummy(struct sport_device *sport)
  248. {
  249. struct dmasg *desc, temp_desc;
  250. unsigned long flags;
  251. BUG_ON(sport->dummy_tx_desc == NULL);
  252. BUG_ON(sport->curr_tx_desc == sport->dummy_tx_desc);
  253. sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc + 1;
  254. /* Shorten the time on last normal descriptor */
  255. local_irq_save(flags);
  256. desc = get_dma_next_desc_ptr(sport->dma_tx_chan);
  257. /* Store the descriptor which will be damaged */
  258. temp_desc = *desc;
  259. desc->x_count = sport->dummy_count / 2;
  260. desc->y_count = 0;
  261. desc->next_desc_addr = sport->dummy_tx_desc;
  262. local_irq_restore(flags);
  263. /* Waiting for dummy buffer descriptor is already hooked*/
  264. while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) - \
  265. sizeof(struct dmasg)) != sport->dummy_tx_desc)
  266. continue;
  267. sport->curr_tx_desc = sport->dummy_tx_desc;
  268. /* Restore the damaged descriptor */
  269. *desc = temp_desc;
  270. return 0;
  271. }
  272. int sport_tx_start(struct sport_device *sport)
  273. {
  274. unsigned long flags;
  275. pr_debug("%s: tx_run:%d, rx_run:%d\n", __func__,
  276. sport->tx_run, sport->rx_run);
  277. if (sport->tx_run)
  278. return -EBUSY;
  279. if (sport->rx_run) {
  280. BUG_ON(sport->dma_tx_desc == NULL);
  281. BUG_ON(sport->curr_tx_desc != sport->dummy_tx_desc);
  282. /* Hook the normal buffer descriptor */
  283. local_irq_save(flags);
  284. while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) -
  285. sizeof(struct dmasg)) != sport->dummy_tx_desc)
  286. continue;
  287. sport->dummy_tx_desc->next_desc_addr = sport->dma_tx_desc;
  288. local_irq_restore(flags);
  289. sport->curr_tx_desc = sport->dma_tx_desc;
  290. } else {
  291. sport_tx_dma_start(sport, 0);
  292. /* Let rx dma run the dummy buffer */
  293. sport_rx_dma_start(sport, 1);
  294. sport_start(sport);
  295. }
  296. sport->tx_run = 1;
  297. return 0;
  298. }
  299. EXPORT_SYMBOL(sport_tx_start);
  300. int sport_tx_stop(struct sport_device *sport)
  301. {
  302. if (!sport->tx_run)
  303. return 0;
  304. if (sport->rx_run) {
  305. /* RX is still running, hook the dummy buffer */
  306. sport_hook_tx_dummy(sport);
  307. } else {
  308. /* Both rx and tx dma stopped */
  309. sport_stop(sport);
  310. sport->curr_rx_desc = NULL;
  311. sport->curr_tx_desc = NULL;
  312. }
  313. sport->tx_run = 0;
  314. return 0;
  315. }
  316. EXPORT_SYMBOL(sport_tx_stop);
  317. static inline int compute_wdsize(size_t wdsize)
  318. {
  319. switch (wdsize) {
  320. case 1:
  321. return WDSIZE_8;
  322. case 2:
  323. return WDSIZE_16;
  324. case 4:
  325. default:
  326. return WDSIZE_32;
  327. }
  328. }
  329. int sport_config_rx_dma(struct sport_device *sport, void *buf,
  330. int fragcount, size_t fragsize)
  331. {
  332. unsigned int x_count;
  333. unsigned int y_count;
  334. unsigned int cfg;
  335. dma_addr_t addr;
  336. pr_debug("%s buf:%p, frag:%d, fragsize:0x%lx\n", __func__, \
  337. buf, fragcount, fragsize);
  338. x_count = fragsize / sport->wdsize;
  339. y_count = 0;
  340. /* for fragments larger than 64k words we use 2d dma,
  341. * denote fragecount as two numbers' mutliply and both of them
  342. * are less than 64k.*/
  343. if (x_count >= 0x10000) {
  344. int i, count = x_count;
  345. for (i = 16; i > 0; i--) {
  346. x_count = 1 << i;
  347. if ((count & (x_count - 1)) == 0) {
  348. y_count = count >> i;
  349. if (y_count < 0x10000)
  350. break;
  351. }
  352. }
  353. if (i == 0)
  354. return -EINVAL;
  355. }
  356. pr_debug("%s(x_count:0x%x, y_count:0x%x)\n", __func__,
  357. x_count, y_count);
  358. if (sport->dma_rx_desc)
  359. dma_free_coherent(NULL, sport->rx_desc_bytes,
  360. sport->dma_rx_desc, 0);
  361. /* Allocate a new descritor ring as current one. */
  362. sport->dma_rx_desc = dma_alloc_coherent(NULL, \
  363. fragcount * sizeof(struct dmasg), &addr, 0);
  364. sport->rx_desc_bytes = fragcount * sizeof(struct dmasg);
  365. if (!sport->dma_rx_desc) {
  366. pr_err("Failed to allocate memory for rx desc\n");
  367. return -ENOMEM;
  368. }
  369. sport->rx_buf = buf;
  370. sport->rx_fragsize = fragsize;
  371. sport->rx_frags = fragcount;
  372. cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | WNR | \
  373. (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
  374. if (y_count != 0)
  375. cfg |= DMA2D;
  376. setup_desc(sport->dma_rx_desc, buf, fragcount, fragsize,
  377. cfg|DMAEN, x_count, y_count, sport->wdsize);
  378. return 0;
  379. }
  380. EXPORT_SYMBOL(sport_config_rx_dma);
  381. int sport_config_tx_dma(struct sport_device *sport, void *buf, \
  382. int fragcount, size_t fragsize)
  383. {
  384. unsigned int x_count;
  385. unsigned int y_count;
  386. unsigned int cfg;
  387. dma_addr_t addr;
  388. pr_debug("%s buf:%p, fragcount:%d, fragsize:0x%lx\n",
  389. __func__, buf, fragcount, fragsize);
  390. x_count = fragsize/sport->wdsize;
  391. y_count = 0;
  392. /* for fragments larger than 64k words we use 2d dma,
  393. * denote fragecount as two numbers' mutliply and both of them
  394. * are less than 64k.*/
  395. if (x_count >= 0x10000) {
  396. int i, count = x_count;
  397. for (i = 16; i > 0; i--) {
  398. x_count = 1 << i;
  399. if ((count & (x_count - 1)) == 0) {
  400. y_count = count >> i;
  401. if (y_count < 0x10000)
  402. break;
  403. }
  404. }
  405. if (i == 0)
  406. return -EINVAL;
  407. }
  408. pr_debug("%s x_count:0x%x, y_count:0x%x\n", __func__,
  409. x_count, y_count);
  410. if (sport->dma_tx_desc) {
  411. dma_free_coherent(NULL, sport->tx_desc_bytes, \
  412. sport->dma_tx_desc, 0);
  413. }
  414. sport->dma_tx_desc = dma_alloc_coherent(NULL, \
  415. fragcount * sizeof(struct dmasg), &addr, 0);
  416. sport->tx_desc_bytes = fragcount * sizeof(struct dmasg);
  417. if (!sport->dma_tx_desc) {
  418. pr_err("Failed to allocate memory for tx desc\n");
  419. return -ENOMEM;
  420. }
  421. sport->tx_buf = buf;
  422. sport->tx_fragsize = fragsize;
  423. sport->tx_frags = fragcount;
  424. cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | \
  425. (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
  426. if (y_count != 0)
  427. cfg |= DMA2D;
  428. setup_desc(sport->dma_tx_desc, buf, fragcount, fragsize,
  429. cfg|DMAEN, x_count, y_count, sport->wdsize);
  430. return 0;
  431. }
  432. EXPORT_SYMBOL(sport_config_tx_dma);
  433. /* setup dummy dma descriptor ring, which don't generate interrupts,
  434. * the x_modify is set to 0 */
  435. static int sport_config_rx_dummy(struct sport_device *sport)
  436. {
  437. struct dmasg *desc;
  438. unsigned config;
  439. pr_debug("%s entered\n", __func__);
  440. if (L1_DATA_A_LENGTH)
  441. desc = l1_data_sram_zalloc(2 * sizeof(*desc));
  442. else {
  443. dma_addr_t addr;
  444. desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
  445. memset(desc, 0, 2 * sizeof(*desc));
  446. }
  447. if (desc == NULL) {
  448. pr_err("Failed to allocate memory for dummy rx desc\n");
  449. return -ENOMEM;
  450. }
  451. sport->dummy_rx_desc = desc;
  452. desc->start_addr = (unsigned long)sport->dummy_buf;
  453. config = DMAFLOW_LARGE | NDSIZE_9 | compute_wdsize(sport->wdsize)
  454. | WNR | DMAEN;
  455. desc->cfg = config;
  456. desc->x_count = sport->dummy_count/sport->wdsize;
  457. desc->x_modify = sport->wdsize;
  458. desc->y_count = 0;
  459. desc->y_modify = 0;
  460. memcpy(desc+1, desc, sizeof(*desc));
  461. desc->next_desc_addr = desc + 1;
  462. desc[1].next_desc_addr = desc;
  463. return 0;
  464. }
  465. static int sport_config_tx_dummy(struct sport_device *sport)
  466. {
  467. struct dmasg *desc;
  468. unsigned int config;
  469. pr_debug("%s entered\n", __func__);
  470. if (L1_DATA_A_LENGTH)
  471. desc = l1_data_sram_zalloc(2 * sizeof(*desc));
  472. else {
  473. dma_addr_t addr;
  474. desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
  475. memset(desc, 0, 2 * sizeof(*desc));
  476. }
  477. if (!desc) {
  478. pr_err("Failed to allocate memory for dummy tx desc\n");
  479. return -ENOMEM;
  480. }
  481. sport->dummy_tx_desc = desc;
  482. desc->start_addr = (unsigned long)sport->dummy_buf + \
  483. sport->dummy_count;
  484. config = DMAFLOW_LARGE | NDSIZE_9 |
  485. compute_wdsize(sport->wdsize) | DMAEN;
  486. desc->cfg = config;
  487. desc->x_count = sport->dummy_count/sport->wdsize;
  488. desc->x_modify = sport->wdsize;
  489. desc->y_count = 0;
  490. desc->y_modify = 0;
  491. memcpy(desc+1, desc, sizeof(*desc));
  492. desc->next_desc_addr = desc + 1;
  493. desc[1].next_desc_addr = desc;
  494. return 0;
  495. }
  496. unsigned long sport_curr_offset_rx(struct sport_device *sport)
  497. {
  498. unsigned long curr = get_dma_curr_addr(sport->dma_rx_chan);
  499. return (unsigned char *)curr - sport->rx_buf;
  500. }
  501. EXPORT_SYMBOL(sport_curr_offset_rx);
  502. unsigned long sport_curr_offset_tx(struct sport_device *sport)
  503. {
  504. unsigned long curr = get_dma_curr_addr(sport->dma_tx_chan);
  505. return (unsigned char *)curr - sport->tx_buf;
  506. }
  507. EXPORT_SYMBOL(sport_curr_offset_tx);
  508. void sport_incfrag(struct sport_device *sport, int *frag, int tx)
  509. {
  510. ++(*frag);
  511. if (tx == 1 && *frag == sport->tx_frags)
  512. *frag = 0;
  513. if (tx == 0 && *frag == sport->rx_frags)
  514. *frag = 0;
  515. }
  516. EXPORT_SYMBOL(sport_incfrag);
  517. void sport_decfrag(struct sport_device *sport, int *frag, int tx)
  518. {
  519. --(*frag);
  520. if (tx == 1 && *frag == 0)
  521. *frag = sport->tx_frags;
  522. if (tx == 0 && *frag == 0)
  523. *frag = sport->rx_frags;
  524. }
  525. EXPORT_SYMBOL(sport_decfrag);
  526. static int sport_check_status(struct sport_device *sport,
  527. unsigned int *sport_stat,
  528. unsigned int *rx_stat,
  529. unsigned int *tx_stat)
  530. {
  531. int status = 0;
  532. if (sport_stat) {
  533. SSYNC();
  534. status = sport->regs->stat;
  535. if (status & (TOVF|TUVF|ROVF|RUVF))
  536. sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
  537. SSYNC();
  538. *sport_stat = status;
  539. }
  540. if (rx_stat) {
  541. SSYNC();
  542. status = get_dma_curr_irqstat(sport->dma_rx_chan);
  543. if (status & (DMA_DONE|DMA_ERR))
  544. clear_dma_irqstat(sport->dma_rx_chan);
  545. SSYNC();
  546. *rx_stat = status;
  547. }
  548. if (tx_stat) {
  549. SSYNC();
  550. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  551. if (status & (DMA_DONE|DMA_ERR))
  552. clear_dma_irqstat(sport->dma_tx_chan);
  553. SSYNC();
  554. *tx_stat = status;
  555. }
  556. return 0;
  557. }
  558. int sport_dump_stat(struct sport_device *sport, char *buf, size_t len)
  559. {
  560. int ret;
  561. ret = snprintf(buf, len,
  562. "sts: 0x%04x\n"
  563. "rx dma %d sts: 0x%04x tx dma %d sts: 0x%04x\n",
  564. sport->regs->stat,
  565. sport->dma_rx_chan,
  566. get_dma_curr_irqstat(sport->dma_rx_chan),
  567. sport->dma_tx_chan,
  568. get_dma_curr_irqstat(sport->dma_tx_chan));
  569. buf += ret;
  570. len -= ret;
  571. ret += snprintf(buf, len,
  572. "curr_rx_desc:0x%p, curr_tx_desc:0x%p\n"
  573. "dma_rx_desc:0x%p, dma_tx_desc:0x%p\n"
  574. "dummy_rx_desc:0x%p, dummy_tx_desc:0x%p\n",
  575. sport->curr_rx_desc, sport->curr_tx_desc,
  576. sport->dma_rx_desc, sport->dma_tx_desc,
  577. sport->dummy_rx_desc, sport->dummy_tx_desc);
  578. return ret;
  579. }
  580. static irqreturn_t rx_handler(int irq, void *dev_id)
  581. {
  582. unsigned int rx_stat;
  583. struct sport_device *sport = dev_id;
  584. pr_debug("%s enter\n", __func__);
  585. sport_check_status(sport, NULL, &rx_stat, NULL);
  586. if (!(rx_stat & DMA_DONE))
  587. pr_err("rx dma is already stopped\n");
  588. if (sport->rx_callback) {
  589. sport->rx_callback(sport->rx_data);
  590. return IRQ_HANDLED;
  591. }
  592. return IRQ_NONE;
  593. }
  594. static irqreturn_t tx_handler(int irq, void *dev_id)
  595. {
  596. unsigned int tx_stat;
  597. struct sport_device *sport = dev_id;
  598. pr_debug("%s enter\n", __func__);
  599. sport_check_status(sport, NULL, NULL, &tx_stat);
  600. if (!(tx_stat & DMA_DONE)) {
  601. pr_err("tx dma is already stopped\n");
  602. return IRQ_HANDLED;
  603. }
  604. if (sport->tx_callback) {
  605. sport->tx_callback(sport->tx_data);
  606. return IRQ_HANDLED;
  607. }
  608. return IRQ_NONE;
  609. }
  610. static irqreturn_t err_handler(int irq, void *dev_id)
  611. {
  612. unsigned int status = 0;
  613. struct sport_device *sport = dev_id;
  614. pr_debug("%s\n", __func__);
  615. if (sport_check_status(sport, &status, NULL, NULL)) {
  616. pr_err("error checking status ??");
  617. return IRQ_NONE;
  618. }
  619. if (status & (TOVF|TUVF|ROVF|RUVF)) {
  620. pr_info("sport status error:%s%s%s%s\n",
  621. status & TOVF ? " TOVF" : "",
  622. status & TUVF ? " TUVF" : "",
  623. status & ROVF ? " ROVF" : "",
  624. status & RUVF ? " RUVF" : "");
  625. if (status & TOVF || status & TUVF) {
  626. disable_dma(sport->dma_tx_chan);
  627. if (sport->tx_run)
  628. sport_tx_dma_start(sport, 0);
  629. else
  630. sport_tx_dma_start(sport, 1);
  631. enable_dma(sport->dma_tx_chan);
  632. } else {
  633. disable_dma(sport->dma_rx_chan);
  634. if (sport->rx_run)
  635. sport_rx_dma_start(sport, 0);
  636. else
  637. sport_rx_dma_start(sport, 1);
  638. enable_dma(sport->dma_rx_chan);
  639. }
  640. }
  641. status = sport->regs->stat;
  642. if (status & (TOVF|TUVF|ROVF|RUVF))
  643. sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
  644. SSYNC();
  645. if (sport->err_callback)
  646. sport->err_callback(sport->err_data);
  647. return IRQ_HANDLED;
  648. }
  649. int sport_set_rx_callback(struct sport_device *sport,
  650. void (*rx_callback)(void *), void *rx_data)
  651. {
  652. BUG_ON(rx_callback == NULL);
  653. sport->rx_callback = rx_callback;
  654. sport->rx_data = rx_data;
  655. return 0;
  656. }
  657. EXPORT_SYMBOL(sport_set_rx_callback);
  658. int sport_set_tx_callback(struct sport_device *sport,
  659. void (*tx_callback)(void *), void *tx_data)
  660. {
  661. BUG_ON(tx_callback == NULL);
  662. sport->tx_callback = tx_callback;
  663. sport->tx_data = tx_data;
  664. return 0;
  665. }
  666. EXPORT_SYMBOL(sport_set_tx_callback);
  667. int sport_set_err_callback(struct sport_device *sport,
  668. void (*err_callback)(void *), void *err_data)
  669. {
  670. BUG_ON(err_callback == NULL);
  671. sport->err_callback = err_callback;
  672. sport->err_data = err_data;
  673. return 0;
  674. }
  675. EXPORT_SYMBOL(sport_set_err_callback);
  676. static int sport_config_pdev(struct platform_device *pdev, struct sport_param *param)
  677. {
  678. /* Extract settings from platform data */
  679. struct device *dev = &pdev->dev;
  680. struct bfin_snd_platform_data *pdata = dev->platform_data;
  681. struct resource *res;
  682. param->num = pdev->id;
  683. if (!pdata) {
  684. dev_err(dev, "no platform_data\n");
  685. return -ENODEV;
  686. }
  687. param->pin_req = pdata->pin_req;
  688. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  689. if (!res) {
  690. dev_err(dev, "no MEM resource\n");
  691. return -ENODEV;
  692. }
  693. param->regs = (struct sport_register *)res->start;
  694. /* first RX, then TX */
  695. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  696. if (!res) {
  697. dev_err(dev, "no rx DMA resource\n");
  698. return -ENODEV;
  699. }
  700. param->dma_rx_chan = res->start;
  701. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  702. if (!res) {
  703. dev_err(dev, "no tx DMA resource\n");
  704. return -ENODEV;
  705. }
  706. param->dma_tx_chan = res->start;
  707. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  708. if (!res) {
  709. dev_err(dev, "no irq resource\n");
  710. return -ENODEV;
  711. }
  712. param->err_irq = res->start;
  713. return 0;
  714. }
  715. struct sport_device *sport_init(struct platform_device *pdev,
  716. unsigned int wdsize, unsigned int dummy_count, size_t priv_size)
  717. {
  718. struct device *dev = &pdev->dev;
  719. struct sport_param param;
  720. struct sport_device *sport;
  721. int ret;
  722. dev_dbg(dev, "%s enter\n", __func__);
  723. param.wdsize = wdsize;
  724. param.dummy_count = dummy_count;
  725. BUG_ON(param.wdsize == 0 || param.dummy_count == 0);
  726. ret = sport_config_pdev(pdev, &param);
  727. if (ret)
  728. return NULL;
  729. if (peripheral_request_list(param.pin_req, "soc-audio")) {
  730. dev_err(dev, "requesting Peripherals failed\n");
  731. return NULL;
  732. }
  733. sport = kzalloc(sizeof(*sport), GFP_KERNEL);
  734. if (!sport) {
  735. dev_err(dev, "failed to allocate for sport device\n");
  736. goto __init_err0;
  737. }
  738. sport->num = param.num;
  739. sport->dma_rx_chan = param.dma_rx_chan;
  740. sport->dma_tx_chan = param.dma_tx_chan;
  741. sport->err_irq = param.err_irq;
  742. sport->regs = param.regs;
  743. sport->pin_req = param.pin_req;
  744. if (request_dma(sport->dma_rx_chan, "SPORT RX Data") == -EBUSY) {
  745. dev_err(dev, "failed to request RX dma %d\n", sport->dma_rx_chan);
  746. goto __init_err1;
  747. }
  748. if (set_dma_callback(sport->dma_rx_chan, rx_handler, sport) != 0) {
  749. dev_err(dev, "failed to request RX irq %d\n", sport->dma_rx_chan);
  750. goto __init_err2;
  751. }
  752. if (request_dma(sport->dma_tx_chan, "SPORT TX Data") == -EBUSY) {
  753. dev_err(dev, "failed to request TX dma %d\n", sport->dma_tx_chan);
  754. goto __init_err2;
  755. }
  756. if (set_dma_callback(sport->dma_tx_chan, tx_handler, sport) != 0) {
  757. dev_err(dev, "failed to request TX irq %d\n", sport->dma_tx_chan);
  758. goto __init_err3;
  759. }
  760. if (request_irq(sport->err_irq, err_handler, IRQF_SHARED, "SPORT err",
  761. sport) < 0) {
  762. dev_err(dev, "failed to request err irq %d\n", sport->err_irq);
  763. goto __init_err3;
  764. }
  765. dev_info(dev, "dma rx:%d tx:%d, err irq:%d, regs:%p\n",
  766. sport->dma_rx_chan, sport->dma_tx_chan,
  767. sport->err_irq, sport->regs);
  768. sport->wdsize = param.wdsize;
  769. sport->dummy_count = param.dummy_count;
  770. sport->private_data = kzalloc(priv_size, GFP_KERNEL);
  771. if (!sport->private_data) {
  772. dev_err(dev, "could not alloc priv data %zu bytes\n", priv_size);
  773. goto __init_err4;
  774. }
  775. if (L1_DATA_A_LENGTH)
  776. sport->dummy_buf = l1_data_sram_zalloc(param.dummy_count * 2);
  777. else
  778. sport->dummy_buf = kzalloc(param.dummy_count * 2, GFP_KERNEL);
  779. if (sport->dummy_buf == NULL) {
  780. dev_err(dev, "failed to allocate dummy buffer\n");
  781. goto __error1;
  782. }
  783. ret = sport_config_rx_dummy(sport);
  784. if (ret) {
  785. dev_err(dev, "failed to config rx dummy ring\n");
  786. goto __error2;
  787. }
  788. ret = sport_config_tx_dummy(sport);
  789. if (ret) {
  790. dev_err(dev, "failed to config tx dummy ring\n");
  791. goto __error3;
  792. }
  793. platform_set_drvdata(pdev, sport);
  794. return sport;
  795. __error3:
  796. if (L1_DATA_A_LENGTH)
  797. l1_data_sram_free(sport->dummy_rx_desc);
  798. else
  799. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  800. sport->dummy_rx_desc, 0);
  801. __error2:
  802. if (L1_DATA_A_LENGTH)
  803. l1_data_sram_free(sport->dummy_buf);
  804. else
  805. kfree(sport->dummy_buf);
  806. __error1:
  807. kfree(sport->private_data);
  808. __init_err4:
  809. free_irq(sport->err_irq, sport);
  810. __init_err3:
  811. free_dma(sport->dma_tx_chan);
  812. __init_err2:
  813. free_dma(sport->dma_rx_chan);
  814. __init_err1:
  815. kfree(sport);
  816. __init_err0:
  817. peripheral_free_list(param.pin_req);
  818. return NULL;
  819. }
  820. EXPORT_SYMBOL(sport_init);
  821. void sport_done(struct sport_device *sport)
  822. {
  823. if (sport == NULL)
  824. return;
  825. sport_stop(sport);
  826. if (sport->dma_rx_desc)
  827. dma_free_coherent(NULL, sport->rx_desc_bytes,
  828. sport->dma_rx_desc, 0);
  829. if (sport->dma_tx_desc)
  830. dma_free_coherent(NULL, sport->tx_desc_bytes,
  831. sport->dma_tx_desc, 0);
  832. #if L1_DATA_A_LENGTH != 0
  833. l1_data_sram_free(sport->dummy_rx_desc);
  834. l1_data_sram_free(sport->dummy_tx_desc);
  835. l1_data_sram_free(sport->dummy_buf);
  836. #else
  837. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  838. sport->dummy_rx_desc, 0);
  839. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  840. sport->dummy_tx_desc, 0);
  841. kfree(sport->dummy_buf);
  842. #endif
  843. free_dma(sport->dma_rx_chan);
  844. free_dma(sport->dma_tx_chan);
  845. free_irq(sport->err_irq, sport);
  846. kfree(sport->private_data);
  847. peripheral_free_list(sport->pin_req);
  848. kfree(sport);
  849. }
  850. EXPORT_SYMBOL(sport_done);
  851. /*
  852. * It is only used to send several bytes when dma is not enabled
  853. * sport controller is configured but not enabled.
  854. * Multichannel cannot works with pio mode */
  855. /* Used by ac97 to write and read codec register */
  856. int sport_send_and_recv(struct sport_device *sport, u8 *out_data, \
  857. u8 *in_data, int len)
  858. {
  859. unsigned short dma_config;
  860. unsigned short status;
  861. unsigned long flags;
  862. unsigned long wait = 0;
  863. pr_debug("%s enter, out_data:%p, in_data:%p len:%d\n", \
  864. __func__, out_data, in_data, len);
  865. pr_debug("tcr1:0x%04x, tcr2:0x%04x, tclkdiv:0x%04x, tfsdiv:0x%04x\n"
  866. "mcmc1:0x%04x, mcmc2:0x%04x\n",
  867. sport->regs->tcr1, sport->regs->tcr2,
  868. sport->regs->tclkdiv, sport->regs->tfsdiv,
  869. sport->regs->mcmc1, sport->regs->mcmc2);
  870. flush_dcache_range((unsigned)out_data, (unsigned)(out_data + len));
  871. /* Enable tx dma */
  872. dma_config = (RESTART | WDSIZE_16 | DI_EN);
  873. set_dma_start_addr(sport->dma_tx_chan, (unsigned long)out_data);
  874. set_dma_x_count(sport->dma_tx_chan, len/2);
  875. set_dma_x_modify(sport->dma_tx_chan, 2);
  876. set_dma_config(sport->dma_tx_chan, dma_config);
  877. enable_dma(sport->dma_tx_chan);
  878. if (in_data != NULL) {
  879. invalidate_dcache_range((unsigned)in_data, \
  880. (unsigned)(in_data + len));
  881. /* Enable rx dma */
  882. dma_config = (RESTART | WDSIZE_16 | WNR | DI_EN);
  883. set_dma_start_addr(sport->dma_rx_chan, (unsigned long)in_data);
  884. set_dma_x_count(sport->dma_rx_chan, len/2);
  885. set_dma_x_modify(sport->dma_rx_chan, 2);
  886. set_dma_config(sport->dma_rx_chan, dma_config);
  887. enable_dma(sport->dma_rx_chan);
  888. }
  889. local_irq_save(flags);
  890. sport->regs->tcr1 |= TSPEN;
  891. sport->regs->rcr1 |= RSPEN;
  892. SSYNC();
  893. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  894. while (status & DMA_RUN) {
  895. udelay(1);
  896. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  897. pr_debug("DMA status:0x%04x\n", status);
  898. if (wait++ > 100)
  899. goto __over;
  900. }
  901. status = sport->regs->stat;
  902. wait = 0;
  903. while (!(status & TXHRE)) {
  904. pr_debug("sport status:0x%04x\n", status);
  905. udelay(1);
  906. status = *(unsigned short *)&sport->regs->stat;
  907. if (wait++ > 1000)
  908. goto __over;
  909. }
  910. /* Wait for the last byte sent out */
  911. udelay(20);
  912. pr_debug("sport status:0x%04x\n", status);
  913. __over:
  914. sport->regs->tcr1 &= ~TSPEN;
  915. sport->regs->rcr1 &= ~RSPEN;
  916. SSYNC();
  917. disable_dma(sport->dma_tx_chan);
  918. /* Clear the status */
  919. clear_dma_irqstat(sport->dma_tx_chan);
  920. if (in_data != NULL) {
  921. disable_dma(sport->dma_rx_chan);
  922. clear_dma_irqstat(sport->dma_rx_chan);
  923. }
  924. SSYNC();
  925. local_irq_restore(flags);
  926. return 0;
  927. }
  928. EXPORT_SYMBOL(sport_send_and_recv);
  929. MODULE_AUTHOR("Roy Huang");
  930. MODULE_DESCRIPTION("SPORT driver for ADI Blackfin");
  931. MODULE_LICENSE("GPL");