abdac.c 15 KB

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  1. /*
  2. * Driver for the Atmel on-chip Audio Bitstream DAC (ABDAC)
  3. *
  4. * Copyright (C) 2006-2009 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/bitmap.h>
  12. #include <linux/dw_dmac.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/io.h>
  20. #include <sound/core.h>
  21. #include <sound/initval.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/atmel-abdac.h>
  25. /* DAC register offsets */
  26. #define DAC_DATA 0x0000
  27. #define DAC_CTRL 0x0008
  28. #define DAC_INT_MASK 0x000c
  29. #define DAC_INT_EN 0x0010
  30. #define DAC_INT_DIS 0x0014
  31. #define DAC_INT_CLR 0x0018
  32. #define DAC_INT_STATUS 0x001c
  33. /* Bitfields in CTRL */
  34. #define DAC_SWAP_OFFSET 30
  35. #define DAC_SWAP_SIZE 1
  36. #define DAC_EN_OFFSET 31
  37. #define DAC_EN_SIZE 1
  38. /* Bitfields in INT_MASK/INT_EN/INT_DIS/INT_STATUS/INT_CLR */
  39. #define DAC_UNDERRUN_OFFSET 28
  40. #define DAC_UNDERRUN_SIZE 1
  41. #define DAC_TX_READY_OFFSET 29
  42. #define DAC_TX_READY_SIZE 1
  43. /* Bit manipulation macros */
  44. #define DAC_BIT(name) \
  45. (1 << DAC_##name##_OFFSET)
  46. #define DAC_BF(name, value) \
  47. (((value) & ((1 << DAC_##name##_SIZE) - 1)) \
  48. << DAC_##name##_OFFSET)
  49. #define DAC_BFEXT(name, value) \
  50. (((value) >> DAC_##name##_OFFSET) \
  51. & ((1 << DAC_##name##_SIZE) - 1))
  52. #define DAC_BFINS(name, value, old) \
  53. (((old) & ~(((1 << DAC_##name##_SIZE) - 1) \
  54. << DAC_##name##_OFFSET)) \
  55. | DAC_BF(name, value))
  56. /* Register access macros */
  57. #define dac_readl(port, reg) \
  58. __raw_readl((port)->regs + DAC_##reg)
  59. #define dac_writel(port, reg, value) \
  60. __raw_writel((value), (port)->regs + DAC_##reg)
  61. /*
  62. * ABDAC supports a maximum of 6 different rates from a generic clock. The
  63. * generic clock has a power of two divider, which gives 6 steps from 192 kHz
  64. * to 5112 Hz.
  65. */
  66. #define MAX_NUM_RATES 6
  67. /* ALSA seems to use rates between 192000 Hz and 5112 Hz. */
  68. #define RATE_MAX 192000
  69. #define RATE_MIN 5112
  70. enum {
  71. DMA_READY = 0,
  72. };
  73. struct atmel_abdac_dma {
  74. struct dma_chan *chan;
  75. struct dw_cyclic_desc *cdesc;
  76. };
  77. struct atmel_abdac {
  78. struct clk *pclk;
  79. struct clk *sample_clk;
  80. struct platform_device *pdev;
  81. struct atmel_abdac_dma dma;
  82. struct snd_pcm_hw_constraint_list constraints_rates;
  83. struct snd_pcm_substream *substream;
  84. struct snd_card *card;
  85. struct snd_pcm *pcm;
  86. void __iomem *regs;
  87. unsigned long flags;
  88. unsigned int rates[MAX_NUM_RATES];
  89. unsigned int rates_num;
  90. int irq;
  91. };
  92. #define get_dac(card) ((struct atmel_abdac *)(card)->private_data)
  93. /* This function is called by the DMA driver. */
  94. static void atmel_abdac_dma_period_done(void *arg)
  95. {
  96. struct atmel_abdac *dac = arg;
  97. snd_pcm_period_elapsed(dac->substream);
  98. }
  99. static int atmel_abdac_prepare_dma(struct atmel_abdac *dac,
  100. struct snd_pcm_substream *substream,
  101. enum dma_data_direction direction)
  102. {
  103. struct dma_chan *chan = dac->dma.chan;
  104. struct dw_cyclic_desc *cdesc;
  105. struct snd_pcm_runtime *runtime = substream->runtime;
  106. unsigned long buffer_len, period_len;
  107. /*
  108. * We don't do DMA on "complex" transfers, i.e. with
  109. * non-halfword-aligned buffers or lengths.
  110. */
  111. if (runtime->dma_addr & 1 || runtime->buffer_size & 1) {
  112. dev_dbg(&dac->pdev->dev, "too complex transfer\n");
  113. return -EINVAL;
  114. }
  115. buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
  116. period_len = frames_to_bytes(runtime, runtime->period_size);
  117. cdesc = dw_dma_cyclic_prep(chan, runtime->dma_addr, buffer_len,
  118. period_len, DMA_TO_DEVICE);
  119. if (IS_ERR(cdesc)) {
  120. dev_dbg(&dac->pdev->dev, "could not prepare cyclic DMA\n");
  121. return PTR_ERR(cdesc);
  122. }
  123. cdesc->period_callback = atmel_abdac_dma_period_done;
  124. cdesc->period_callback_param = dac;
  125. dac->dma.cdesc = cdesc;
  126. set_bit(DMA_READY, &dac->flags);
  127. return 0;
  128. }
  129. static struct snd_pcm_hardware atmel_abdac_hw = {
  130. .info = (SNDRV_PCM_INFO_MMAP
  131. | SNDRV_PCM_INFO_MMAP_VALID
  132. | SNDRV_PCM_INFO_INTERLEAVED
  133. | SNDRV_PCM_INFO_BLOCK_TRANSFER
  134. | SNDRV_PCM_INFO_RESUME
  135. | SNDRV_PCM_INFO_PAUSE),
  136. .formats = (SNDRV_PCM_FMTBIT_S16_BE),
  137. .rates = (SNDRV_PCM_RATE_KNOT),
  138. .rate_min = RATE_MIN,
  139. .rate_max = RATE_MAX,
  140. .channels_min = 2,
  141. .channels_max = 2,
  142. .buffer_bytes_max = 64 * 4096,
  143. .period_bytes_min = 4096,
  144. .period_bytes_max = 4096,
  145. .periods_min = 6,
  146. .periods_max = 64,
  147. };
  148. static int atmel_abdac_open(struct snd_pcm_substream *substream)
  149. {
  150. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  151. dac->substream = substream;
  152. atmel_abdac_hw.rate_max = dac->rates[dac->rates_num - 1];
  153. atmel_abdac_hw.rate_min = dac->rates[0];
  154. substream->runtime->hw = atmel_abdac_hw;
  155. return snd_pcm_hw_constraint_list(substream->runtime, 0,
  156. SNDRV_PCM_HW_PARAM_RATE, &dac->constraints_rates);
  157. }
  158. static int atmel_abdac_close(struct snd_pcm_substream *substream)
  159. {
  160. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  161. dac->substream = NULL;
  162. return 0;
  163. }
  164. static int atmel_abdac_hw_params(struct snd_pcm_substream *substream,
  165. struct snd_pcm_hw_params *hw_params)
  166. {
  167. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  168. int retval;
  169. retval = snd_pcm_lib_malloc_pages(substream,
  170. params_buffer_bytes(hw_params));
  171. if (retval < 0)
  172. return retval;
  173. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  174. if (retval == 1)
  175. if (test_and_clear_bit(DMA_READY, &dac->flags))
  176. dw_dma_cyclic_free(dac->dma.chan);
  177. return retval;
  178. }
  179. static int atmel_abdac_hw_free(struct snd_pcm_substream *substream)
  180. {
  181. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  182. if (test_and_clear_bit(DMA_READY, &dac->flags))
  183. dw_dma_cyclic_free(dac->dma.chan);
  184. return snd_pcm_lib_free_pages(substream);
  185. }
  186. static int atmel_abdac_prepare(struct snd_pcm_substream *substream)
  187. {
  188. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  189. int retval;
  190. retval = clk_set_rate(dac->sample_clk, 256 * substream->runtime->rate);
  191. if (retval)
  192. return retval;
  193. if (!test_bit(DMA_READY, &dac->flags))
  194. retval = atmel_abdac_prepare_dma(dac, substream, DMA_TO_DEVICE);
  195. return retval;
  196. }
  197. static int atmel_abdac_trigger(struct snd_pcm_substream *substream, int cmd)
  198. {
  199. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  200. int retval = 0;
  201. switch (cmd) {
  202. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  203. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  204. case SNDRV_PCM_TRIGGER_START:
  205. clk_enable(dac->sample_clk);
  206. retval = dw_dma_cyclic_start(dac->dma.chan);
  207. if (retval)
  208. goto out;
  209. dac_writel(dac, CTRL, DAC_BIT(EN));
  210. break;
  211. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  212. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  213. case SNDRV_PCM_TRIGGER_STOP:
  214. dw_dma_cyclic_stop(dac->dma.chan);
  215. dac_writel(dac, DATA, 0);
  216. dac_writel(dac, CTRL, 0);
  217. clk_disable(dac->sample_clk);
  218. break;
  219. default:
  220. retval = -EINVAL;
  221. break;
  222. }
  223. out:
  224. return retval;
  225. }
  226. static snd_pcm_uframes_t
  227. atmel_abdac_pointer(struct snd_pcm_substream *substream)
  228. {
  229. struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
  230. struct snd_pcm_runtime *runtime = substream->runtime;
  231. snd_pcm_uframes_t frames;
  232. unsigned long bytes;
  233. bytes = dw_dma_get_src_addr(dac->dma.chan);
  234. bytes -= runtime->dma_addr;
  235. frames = bytes_to_frames(runtime, bytes);
  236. if (frames >= runtime->buffer_size)
  237. frames -= runtime->buffer_size;
  238. return frames;
  239. }
  240. static irqreturn_t abdac_interrupt(int irq, void *dev_id)
  241. {
  242. struct atmel_abdac *dac = dev_id;
  243. u32 status;
  244. status = dac_readl(dac, INT_STATUS);
  245. if (status & DAC_BIT(UNDERRUN)) {
  246. dev_err(&dac->pdev->dev, "underrun detected\n");
  247. dac_writel(dac, INT_CLR, DAC_BIT(UNDERRUN));
  248. } else {
  249. dev_err(&dac->pdev->dev, "spurious interrupt (status=0x%x)\n",
  250. status);
  251. dac_writel(dac, INT_CLR, status);
  252. }
  253. return IRQ_HANDLED;
  254. }
  255. static struct snd_pcm_ops atmel_abdac_ops = {
  256. .open = atmel_abdac_open,
  257. .close = atmel_abdac_close,
  258. .ioctl = snd_pcm_lib_ioctl,
  259. .hw_params = atmel_abdac_hw_params,
  260. .hw_free = atmel_abdac_hw_free,
  261. .prepare = atmel_abdac_prepare,
  262. .trigger = atmel_abdac_trigger,
  263. .pointer = atmel_abdac_pointer,
  264. };
  265. static int __devinit atmel_abdac_pcm_new(struct atmel_abdac *dac)
  266. {
  267. struct snd_pcm_hardware hw = atmel_abdac_hw;
  268. struct snd_pcm *pcm;
  269. int retval;
  270. retval = snd_pcm_new(dac->card, dac->card->shortname,
  271. dac->pdev->id, 1, 0, &pcm);
  272. if (retval)
  273. return retval;
  274. strcpy(pcm->name, dac->card->shortname);
  275. pcm->private_data = dac;
  276. pcm->info_flags = 0;
  277. dac->pcm = pcm;
  278. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &atmel_abdac_ops);
  279. retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  280. &dac->pdev->dev, hw.periods_min * hw.period_bytes_min,
  281. hw.buffer_bytes_max);
  282. return retval;
  283. }
  284. static bool filter(struct dma_chan *chan, void *slave)
  285. {
  286. struct dw_dma_slave *dws = slave;
  287. if (dws->dma_dev == chan->device->dev) {
  288. chan->private = dws;
  289. return true;
  290. } else
  291. return false;
  292. }
  293. static int set_sample_rates(struct atmel_abdac *dac)
  294. {
  295. long new_rate = RATE_MAX;
  296. int retval = -EINVAL;
  297. int index = 0;
  298. /* we start at 192 kHz and work our way down to 5112 Hz */
  299. while (new_rate >= RATE_MIN && index < (MAX_NUM_RATES + 1)) {
  300. new_rate = clk_round_rate(dac->sample_clk, 256 * new_rate);
  301. if (new_rate < 0)
  302. break;
  303. /* make sure we are below the ABDAC clock */
  304. if (new_rate <= clk_get_rate(dac->pclk)) {
  305. dac->rates[index] = new_rate / 256;
  306. index++;
  307. }
  308. /* divide by 256 and then by two to get next rate */
  309. new_rate /= 256 * 2;
  310. }
  311. if (index) {
  312. int i;
  313. /* reverse array, smallest go first */
  314. for (i = 0; i < (index / 2); i++) {
  315. unsigned int tmp = dac->rates[index - 1 - i];
  316. dac->rates[index - 1 - i] = dac->rates[i];
  317. dac->rates[i] = tmp;
  318. }
  319. dac->constraints_rates.count = index;
  320. dac->constraints_rates.list = dac->rates;
  321. dac->constraints_rates.mask = 0;
  322. dac->rates_num = index;
  323. retval = 0;
  324. }
  325. return retval;
  326. }
  327. static int __devinit atmel_abdac_probe(struct platform_device *pdev)
  328. {
  329. struct snd_card *card;
  330. struct atmel_abdac *dac;
  331. struct resource *regs;
  332. struct atmel_abdac_pdata *pdata;
  333. struct clk *pclk;
  334. struct clk *sample_clk;
  335. int retval;
  336. int irq;
  337. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  338. if (!regs) {
  339. dev_dbg(&pdev->dev, "no memory resource\n");
  340. return -ENXIO;
  341. }
  342. irq = platform_get_irq(pdev, 0);
  343. if (irq < 0) {
  344. dev_dbg(&pdev->dev, "could not get IRQ number\n");
  345. return irq;
  346. }
  347. pdata = pdev->dev.platform_data;
  348. if (!pdata) {
  349. dev_dbg(&pdev->dev, "no platform data\n");
  350. return -ENXIO;
  351. }
  352. pclk = clk_get(&pdev->dev, "pclk");
  353. if (IS_ERR(pclk)) {
  354. dev_dbg(&pdev->dev, "no peripheral clock\n");
  355. return PTR_ERR(pclk);
  356. }
  357. sample_clk = clk_get(&pdev->dev, "sample_clk");
  358. if (IS_ERR(sample_clk)) {
  359. dev_dbg(&pdev->dev, "no sample clock\n");
  360. retval = PTR_ERR(sample_clk);
  361. goto out_put_pclk;
  362. }
  363. clk_enable(pclk);
  364. retval = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  365. THIS_MODULE, sizeof(struct atmel_abdac), &card);
  366. if (retval) {
  367. dev_dbg(&pdev->dev, "could not create sound card device\n");
  368. goto out_put_sample_clk;
  369. }
  370. dac = get_dac(card);
  371. dac->irq = irq;
  372. dac->card = card;
  373. dac->pclk = pclk;
  374. dac->sample_clk = sample_clk;
  375. dac->pdev = pdev;
  376. retval = set_sample_rates(dac);
  377. if (retval < 0) {
  378. dev_dbg(&pdev->dev, "could not set supported rates\n");
  379. goto out_free_card;
  380. }
  381. dac->regs = ioremap(regs->start, regs->end - regs->start + 1);
  382. if (!dac->regs) {
  383. dev_dbg(&pdev->dev, "could not remap register memory\n");
  384. goto out_free_card;
  385. }
  386. /* make sure the DAC is silent and disabled */
  387. dac_writel(dac, DATA, 0);
  388. dac_writel(dac, CTRL, 0);
  389. retval = request_irq(irq, abdac_interrupt, 0, "abdac", dac);
  390. if (retval) {
  391. dev_dbg(&pdev->dev, "could not request irq\n");
  392. goto out_unmap_regs;
  393. }
  394. snd_card_set_dev(card, &pdev->dev);
  395. if (pdata->dws.dma_dev) {
  396. struct dw_dma_slave *dws = &pdata->dws;
  397. dma_cap_mask_t mask;
  398. dws->tx_reg = regs->start + DAC_DATA;
  399. dma_cap_zero(mask);
  400. dma_cap_set(DMA_SLAVE, mask);
  401. dac->dma.chan = dma_request_channel(mask, filter, dws);
  402. }
  403. if (!pdata->dws.dma_dev || !dac->dma.chan) {
  404. dev_dbg(&pdev->dev, "DMA not available\n");
  405. retval = -ENODEV;
  406. goto out_unset_card_dev;
  407. }
  408. strcpy(card->driver, "Atmel ABDAC");
  409. strcpy(card->shortname, "Atmel ABDAC");
  410. sprintf(card->longname, "Atmel Audio Bitstream DAC");
  411. retval = atmel_abdac_pcm_new(dac);
  412. if (retval) {
  413. dev_dbg(&pdev->dev, "could not register ABDAC pcm device\n");
  414. goto out_release_dma;
  415. }
  416. retval = snd_card_register(card);
  417. if (retval) {
  418. dev_dbg(&pdev->dev, "could not register sound card\n");
  419. goto out_release_dma;
  420. }
  421. platform_set_drvdata(pdev, card);
  422. dev_info(&pdev->dev, "Atmel ABDAC at 0x%p using %s\n",
  423. dac->regs, dev_name(&dac->dma.chan->dev->device));
  424. return retval;
  425. out_release_dma:
  426. dma_release_channel(dac->dma.chan);
  427. dac->dma.chan = NULL;
  428. out_unset_card_dev:
  429. snd_card_set_dev(card, NULL);
  430. free_irq(irq, dac);
  431. out_unmap_regs:
  432. iounmap(dac->regs);
  433. out_free_card:
  434. snd_card_free(card);
  435. out_put_sample_clk:
  436. clk_put(sample_clk);
  437. clk_disable(pclk);
  438. out_put_pclk:
  439. clk_put(pclk);
  440. return retval;
  441. }
  442. #ifdef CONFIG_PM
  443. static int atmel_abdac_suspend(struct platform_device *pdev, pm_message_t msg)
  444. {
  445. struct snd_card *card = platform_get_drvdata(pdev);
  446. struct atmel_abdac *dac = card->private_data;
  447. dw_dma_cyclic_stop(dac->dma.chan);
  448. clk_disable(dac->sample_clk);
  449. clk_disable(dac->pclk);
  450. return 0;
  451. }
  452. static int atmel_abdac_resume(struct platform_device *pdev)
  453. {
  454. struct snd_card *card = platform_get_drvdata(pdev);
  455. struct atmel_abdac *dac = card->private_data;
  456. clk_enable(dac->pclk);
  457. clk_enable(dac->sample_clk);
  458. if (test_bit(DMA_READY, &dac->flags))
  459. dw_dma_cyclic_start(dac->dma.chan);
  460. return 0;
  461. }
  462. #else
  463. #define atmel_abdac_suspend NULL
  464. #define atmel_abdac_resume NULL
  465. #endif
  466. static int __devexit atmel_abdac_remove(struct platform_device *pdev)
  467. {
  468. struct snd_card *card = platform_get_drvdata(pdev);
  469. struct atmel_abdac *dac = get_dac(card);
  470. clk_put(dac->sample_clk);
  471. clk_disable(dac->pclk);
  472. clk_put(dac->pclk);
  473. dma_release_channel(dac->dma.chan);
  474. dac->dma.chan = NULL;
  475. snd_card_set_dev(card, NULL);
  476. iounmap(dac->regs);
  477. free_irq(dac->irq, dac);
  478. snd_card_free(card);
  479. platform_set_drvdata(pdev, NULL);
  480. return 0;
  481. }
  482. static struct platform_driver atmel_abdac_driver = {
  483. .remove = __devexit_p(atmel_abdac_remove),
  484. .driver = {
  485. .name = "atmel_abdac",
  486. },
  487. .suspend = atmel_abdac_suspend,
  488. .resume = atmel_abdac_resume,
  489. };
  490. static int __init atmel_abdac_init(void)
  491. {
  492. return platform_driver_probe(&atmel_abdac_driver,
  493. atmel_abdac_probe);
  494. }
  495. module_init(atmel_abdac_init);
  496. static void __exit atmel_abdac_exit(void)
  497. {
  498. platform_driver_unregister(&atmel_abdac_driver);
  499. }
  500. module_exit(atmel_abdac_exit);
  501. MODULE_LICENSE("GPL");
  502. MODULE_DESCRIPTION("Driver for Atmel Audio Bitstream DAC (ABDAC)");
  503. MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");