mv88e6060.c 6.0 KB

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  1. /*
  2. * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
  3. * Copyright (c) 2008-2009 Marvell Semiconductor
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. */
  10. #include <linux/list.h>
  11. #include <linux/netdevice.h>
  12. #include <linux/phy.h>
  13. #include "dsa_priv.h"
  14. #define REG_PORT(p) (8 + (p))
  15. #define REG_GLOBAL 0x0f
  16. static int reg_read(struct dsa_switch *ds, int addr, int reg)
  17. {
  18. return mdiobus_read(ds->master_mii_bus, ds->pd->sw_addr + addr, reg);
  19. }
  20. #define REG_READ(addr, reg) \
  21. ({ \
  22. int __ret; \
  23. \
  24. __ret = reg_read(ds, addr, reg); \
  25. if (__ret < 0) \
  26. return __ret; \
  27. __ret; \
  28. })
  29. static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
  30. {
  31. return mdiobus_write(ds->master_mii_bus, ds->pd->sw_addr + addr,
  32. reg, val);
  33. }
  34. #define REG_WRITE(addr, reg, val) \
  35. ({ \
  36. int __ret; \
  37. \
  38. __ret = reg_write(ds, addr, reg, val); \
  39. if (__ret < 0) \
  40. return __ret; \
  41. })
  42. static char *mv88e6060_probe(struct mii_bus *bus, int sw_addr)
  43. {
  44. int ret;
  45. ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
  46. if (ret >= 0) {
  47. ret &= 0xfff0;
  48. if (ret == 0x0600)
  49. return "Marvell 88E6060";
  50. }
  51. return NULL;
  52. }
  53. static int mv88e6060_switch_reset(struct dsa_switch *ds)
  54. {
  55. int i;
  56. int ret;
  57. /*
  58. * Set all ports to the disabled state.
  59. */
  60. for (i = 0; i < 6; i++) {
  61. ret = REG_READ(REG_PORT(i), 0x04);
  62. REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  63. }
  64. /*
  65. * Wait for transmit queues to drain.
  66. */
  67. msleep(2);
  68. /*
  69. * Reset the switch.
  70. */
  71. REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
  72. /*
  73. * Wait up to one second for reset to complete.
  74. */
  75. for (i = 0; i < 1000; i++) {
  76. ret = REG_READ(REG_GLOBAL, 0x00);
  77. if ((ret & 0x8000) == 0x0000)
  78. break;
  79. msleep(1);
  80. }
  81. if (i == 1000)
  82. return -ETIMEDOUT;
  83. return 0;
  84. }
  85. static int mv88e6060_setup_global(struct dsa_switch *ds)
  86. {
  87. /*
  88. * Disable discarding of frames with excessive collisions,
  89. * set the maximum frame size to 1536 bytes, and mask all
  90. * interrupt sources.
  91. */
  92. REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
  93. /*
  94. * Enable automatic address learning, set the address
  95. * database size to 1024 entries, and set the default aging
  96. * time to 5 minutes.
  97. */
  98. REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
  99. return 0;
  100. }
  101. static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
  102. {
  103. int addr = REG_PORT(p);
  104. /*
  105. * Do not force flow control, disable Ingress and Egress
  106. * Header tagging, disable VLAN tunneling, and set the port
  107. * state to Forwarding. Additionally, if this is the CPU
  108. * port, enable Ingress and Egress Trailer tagging mode.
  109. */
  110. REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
  111. /*
  112. * Port based VLAN map: give each port its own address
  113. * database, allow the CPU port to talk to each of the 'real'
  114. * ports, and allow each of the 'real' ports to only talk to
  115. * the CPU port.
  116. */
  117. REG_WRITE(addr, 0x06,
  118. ((p & 0xf) << 12) |
  119. (dsa_is_cpu_port(ds, p) ?
  120. ds->phys_port_mask :
  121. (1 << ds->dst->cpu_port)));
  122. /*
  123. * Port Association Vector: when learning source addresses
  124. * of packets, add the address to the address database using
  125. * a port bitmap that has only the bit for this port set and
  126. * the other bits clear.
  127. */
  128. REG_WRITE(addr, 0x0b, 1 << p);
  129. return 0;
  130. }
  131. static int mv88e6060_setup(struct dsa_switch *ds)
  132. {
  133. int i;
  134. int ret;
  135. ret = mv88e6060_switch_reset(ds);
  136. if (ret < 0)
  137. return ret;
  138. /* @@@ initialise atu */
  139. ret = mv88e6060_setup_global(ds);
  140. if (ret < 0)
  141. return ret;
  142. for (i = 0; i < 6; i++) {
  143. ret = mv88e6060_setup_port(ds, i);
  144. if (ret < 0)
  145. return ret;
  146. }
  147. return 0;
  148. }
  149. static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
  150. {
  151. REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
  152. REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
  153. REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
  154. return 0;
  155. }
  156. static int mv88e6060_port_to_phy_addr(int port)
  157. {
  158. if (port >= 0 && port <= 5)
  159. return port;
  160. return -1;
  161. }
  162. static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
  163. {
  164. int addr;
  165. addr = mv88e6060_port_to_phy_addr(port);
  166. if (addr == -1)
  167. return 0xffff;
  168. return reg_read(ds, addr, regnum);
  169. }
  170. static int
  171. mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
  172. {
  173. int addr;
  174. addr = mv88e6060_port_to_phy_addr(port);
  175. if (addr == -1)
  176. return 0xffff;
  177. return reg_write(ds, addr, regnum, val);
  178. }
  179. static void mv88e6060_poll_link(struct dsa_switch *ds)
  180. {
  181. int i;
  182. for (i = 0; i < DSA_MAX_PORTS; i++) {
  183. struct net_device *dev;
  184. int uninitialized_var(port_status);
  185. int link;
  186. int speed;
  187. int duplex;
  188. int fc;
  189. dev = ds->ports[i];
  190. if (dev == NULL)
  191. continue;
  192. link = 0;
  193. if (dev->flags & IFF_UP) {
  194. port_status = reg_read(ds, REG_PORT(i), 0x00);
  195. if (port_status < 0)
  196. continue;
  197. link = !!(port_status & 0x1000);
  198. }
  199. if (!link) {
  200. if (netif_carrier_ok(dev)) {
  201. printk(KERN_INFO "%s: link down\n", dev->name);
  202. netif_carrier_off(dev);
  203. }
  204. continue;
  205. }
  206. speed = (port_status & 0x0100) ? 100 : 10;
  207. duplex = (port_status & 0x0200) ? 1 : 0;
  208. fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
  209. if (!netif_carrier_ok(dev)) {
  210. printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
  211. "flow control %sabled\n", dev->name,
  212. speed, duplex ? "full" : "half",
  213. fc ? "en" : "dis");
  214. netif_carrier_on(dev);
  215. }
  216. }
  217. }
  218. static struct dsa_switch_driver mv88e6060_switch_driver = {
  219. .tag_protocol = htons(ETH_P_TRAILER),
  220. .probe = mv88e6060_probe,
  221. .setup = mv88e6060_setup,
  222. .set_addr = mv88e6060_set_addr,
  223. .phy_read = mv88e6060_phy_read,
  224. .phy_write = mv88e6060_phy_write,
  225. .poll_link = mv88e6060_poll_link,
  226. };
  227. static int __init mv88e6060_init(void)
  228. {
  229. register_switch_driver(&mv88e6060_switch_driver);
  230. return 0;
  231. }
  232. module_init(mv88e6060_init);
  233. static void __exit mv88e6060_cleanup(void)
  234. {
  235. unregister_switch_driver(&mv88e6060_switch_driver);
  236. }
  237. module_exit(mv88e6060_cleanup);