ci13xxx_udc.c 71 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/interrupt.h>
  58. #include <linux/io.h>
  59. #include <linux/irq.h>
  60. #include <linux/kernel.h>
  61. #include <linux/slab.h>
  62. #include <linux/pm_runtime.h>
  63. #include <linux/usb/ch9.h>
  64. #include <linux/usb/gadget.h>
  65. #include <linux/usb/otg.h>
  66. #include "ci13xxx_udc.h"
  67. /******************************************************************************
  68. * DEFINE
  69. *****************************************************************************/
  70. /* ctrl register bank access */
  71. static DEFINE_SPINLOCK(udc_lock);
  72. /* control endpoint description */
  73. static const struct usb_endpoint_descriptor
  74. ctrl_endpt_out_desc = {
  75. .bLength = USB_DT_ENDPOINT_SIZE,
  76. .bDescriptorType = USB_DT_ENDPOINT,
  77. .bEndpointAddress = USB_DIR_OUT,
  78. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  79. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  80. };
  81. static const struct usb_endpoint_descriptor
  82. ctrl_endpt_in_desc = {
  83. .bLength = USB_DT_ENDPOINT_SIZE,
  84. .bDescriptorType = USB_DT_ENDPOINT,
  85. .bEndpointAddress = USB_DIR_IN,
  86. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  87. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  88. };
  89. /* UDC descriptor */
  90. static struct ci13xxx *_udc;
  91. /* Interrupt statistics */
  92. #define ISR_MASK 0x1F
  93. static struct {
  94. u32 test;
  95. u32 ui;
  96. u32 uei;
  97. u32 pci;
  98. u32 uri;
  99. u32 sli;
  100. u32 none;
  101. struct {
  102. u32 cnt;
  103. u32 buf[ISR_MASK+1];
  104. u32 idx;
  105. } hndl;
  106. } isr_statistics;
  107. /**
  108. * ffs_nr: find first (least significant) bit set
  109. * @x: the word to search
  110. *
  111. * This function returns bit number (instead of position)
  112. */
  113. static int ffs_nr(u32 x)
  114. {
  115. int n = ffs(x);
  116. return n ? n-1 : 32;
  117. }
  118. /******************************************************************************
  119. * HW block
  120. *****************************************************************************/
  121. /* register bank descriptor */
  122. static struct {
  123. unsigned lpm; /* is LPM? */
  124. void __iomem *abs; /* bus map offset */
  125. void __iomem *cap; /* bus map offset + CAP offset + CAP data */
  126. size_t size; /* bank size */
  127. } hw_bank;
  128. /* MSM specific */
  129. #define ABS_AHBBURST (0x0090UL)
  130. #define ABS_AHBMODE (0x0098UL)
  131. /* UDC register map */
  132. #define ABS_CAPLENGTH (0x100UL)
  133. #define ABS_HCCPARAMS (0x108UL)
  134. #define ABS_DCCPARAMS (0x124UL)
  135. #define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
  136. /* offset to CAPLENTGH (addr + data) */
  137. #define CAP_USBCMD (0x000UL)
  138. #define CAP_USBSTS (0x004UL)
  139. #define CAP_USBINTR (0x008UL)
  140. #define CAP_DEVICEADDR (0x014UL)
  141. #define CAP_ENDPTLISTADDR (0x018UL)
  142. #define CAP_PORTSC (0x044UL)
  143. #define CAP_DEVLC (0x084UL)
  144. #define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
  145. #define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
  146. #define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
  147. #define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
  148. #define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
  149. #define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
  150. #define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
  151. #define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
  152. /* maximum number of enpoints: valid only after hw_device_reset() */
  153. static unsigned hw_ep_max;
  154. /**
  155. * hw_ep_bit: calculates the bit number
  156. * @num: endpoint number
  157. * @dir: endpoint direction
  158. *
  159. * This function returns bit number
  160. */
  161. static inline int hw_ep_bit(int num, int dir)
  162. {
  163. return num + (dir ? 16 : 0);
  164. }
  165. /**
  166. * hw_aread: reads from register bitfield
  167. * @addr: address relative to bus map
  168. * @mask: bitfield mask
  169. *
  170. * This function returns register bitfield data
  171. */
  172. static u32 hw_aread(u32 addr, u32 mask)
  173. {
  174. return ioread32(addr + hw_bank.abs) & mask;
  175. }
  176. /**
  177. * hw_awrite: writes to register bitfield
  178. * @addr: address relative to bus map
  179. * @mask: bitfield mask
  180. * @data: new data
  181. */
  182. static void hw_awrite(u32 addr, u32 mask, u32 data)
  183. {
  184. iowrite32(hw_aread(addr, ~mask) | (data & mask),
  185. addr + hw_bank.abs);
  186. }
  187. /**
  188. * hw_cread: reads from register bitfield
  189. * @addr: address relative to CAP offset plus content
  190. * @mask: bitfield mask
  191. *
  192. * This function returns register bitfield data
  193. */
  194. static u32 hw_cread(u32 addr, u32 mask)
  195. {
  196. return ioread32(addr + hw_bank.cap) & mask;
  197. }
  198. /**
  199. * hw_cwrite: writes to register bitfield
  200. * @addr: address relative to CAP offset plus content
  201. * @mask: bitfield mask
  202. * @data: new data
  203. */
  204. static void hw_cwrite(u32 addr, u32 mask, u32 data)
  205. {
  206. iowrite32(hw_cread(addr, ~mask) | (data & mask),
  207. addr + hw_bank.cap);
  208. }
  209. /**
  210. * hw_ctest_and_clear: tests & clears register bitfield
  211. * @addr: address relative to CAP offset plus content
  212. * @mask: bitfield mask
  213. *
  214. * This function returns register bitfield data
  215. */
  216. static u32 hw_ctest_and_clear(u32 addr, u32 mask)
  217. {
  218. u32 reg = hw_cread(addr, mask);
  219. iowrite32(reg, addr + hw_bank.cap);
  220. return reg;
  221. }
  222. /**
  223. * hw_ctest_and_write: tests & writes register bitfield
  224. * @addr: address relative to CAP offset plus content
  225. * @mask: bitfield mask
  226. * @data: new data
  227. *
  228. * This function returns register bitfield data
  229. */
  230. static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
  231. {
  232. u32 reg = hw_cread(addr, ~0);
  233. iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
  234. return (reg & mask) >> ffs_nr(mask);
  235. }
  236. static int hw_device_init(void __iomem *base)
  237. {
  238. u32 reg;
  239. /* bank is a module variable */
  240. hw_bank.abs = base;
  241. hw_bank.cap = hw_bank.abs;
  242. hw_bank.cap += ABS_CAPLENGTH;
  243. hw_bank.cap += ioread8(hw_bank.cap);
  244. reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
  245. hw_bank.lpm = reg;
  246. hw_bank.size = hw_bank.cap - hw_bank.abs;
  247. hw_bank.size += CAP_LAST;
  248. hw_bank.size /= sizeof(u32);
  249. reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
  250. hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  251. if (hw_ep_max == 0 || hw_ep_max > ENDPT_MAX)
  252. return -ENODEV;
  253. /* setup lock mode ? */
  254. /* ENDPTSETUPSTAT is '0' by default */
  255. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  256. return 0;
  257. }
  258. /**
  259. * hw_device_reset: resets chip (execute without interruption)
  260. * @base: register base address
  261. *
  262. * This function returns an error code
  263. */
  264. static int hw_device_reset(struct ci13xxx *udc)
  265. {
  266. /* should flush & stop before reset */
  267. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
  268. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  269. hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
  270. while (hw_cread(CAP_USBCMD, USBCMD_RST))
  271. udelay(10); /* not RTOS friendly */
  272. if (udc->udc_driver->notify_event)
  273. udc->udc_driver->notify_event(udc,
  274. CI13XXX_CONTROLLER_RESET_EVENT);
  275. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  276. hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  277. /* USBMODE should be configured step by step */
  278. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  279. hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  280. hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
  281. if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  282. pr_err("cannot enter in device mode");
  283. pr_err("lpm = %i", hw_bank.lpm);
  284. return -ENODEV;
  285. }
  286. return 0;
  287. }
  288. /**
  289. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  290. * without interruption)
  291. * @dma: 0 => disable, !0 => enable and set dma engine
  292. *
  293. * This function returns an error code
  294. */
  295. static int hw_device_state(u32 dma)
  296. {
  297. if (dma) {
  298. hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
  299. /* interrupt, error, port change, reset, sleep/suspend */
  300. hw_cwrite(CAP_USBINTR, ~0,
  301. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  302. hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
  303. } else {
  304. hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
  305. hw_cwrite(CAP_USBINTR, ~0, 0);
  306. }
  307. return 0;
  308. }
  309. /**
  310. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  311. * @num: endpoint number
  312. * @dir: endpoint direction
  313. *
  314. * This function returns an error code
  315. */
  316. static int hw_ep_flush(int num, int dir)
  317. {
  318. int n = hw_ep_bit(num, dir);
  319. do {
  320. /* flush any pending transfer */
  321. hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
  322. while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
  323. cpu_relax();
  324. } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
  325. return 0;
  326. }
  327. /**
  328. * hw_ep_disable: disables endpoint (execute without interruption)
  329. * @num: endpoint number
  330. * @dir: endpoint direction
  331. *
  332. * This function returns an error code
  333. */
  334. static int hw_ep_disable(int num, int dir)
  335. {
  336. hw_ep_flush(num, dir);
  337. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
  338. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  339. return 0;
  340. }
  341. /**
  342. * hw_ep_enable: enables endpoint (execute without interruption)
  343. * @num: endpoint number
  344. * @dir: endpoint direction
  345. * @type: endpoint type
  346. *
  347. * This function returns an error code
  348. */
  349. static int hw_ep_enable(int num, int dir, int type)
  350. {
  351. u32 mask, data;
  352. if (dir) {
  353. mask = ENDPTCTRL_TXT; /* type */
  354. data = type << ffs_nr(mask);
  355. mask |= ENDPTCTRL_TXS; /* unstall */
  356. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  357. data |= ENDPTCTRL_TXR;
  358. mask |= ENDPTCTRL_TXE; /* enable */
  359. data |= ENDPTCTRL_TXE;
  360. } else {
  361. mask = ENDPTCTRL_RXT; /* type */
  362. data = type << ffs_nr(mask);
  363. mask |= ENDPTCTRL_RXS; /* unstall */
  364. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  365. data |= ENDPTCTRL_RXR;
  366. mask |= ENDPTCTRL_RXE; /* enable */
  367. data |= ENDPTCTRL_RXE;
  368. }
  369. hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
  370. return 0;
  371. }
  372. /**
  373. * hw_ep_get_halt: return endpoint halt status
  374. * @num: endpoint number
  375. * @dir: endpoint direction
  376. *
  377. * This function returns 1 if endpoint halted
  378. */
  379. static int hw_ep_get_halt(int num, int dir)
  380. {
  381. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  382. return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
  383. }
  384. /**
  385. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  386. * interruption)
  387. * @n: bit number (endpoint)
  388. *
  389. * This function returns setup status
  390. */
  391. static int hw_test_and_clear_setup_status(int n)
  392. {
  393. return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
  394. }
  395. /**
  396. * hw_ep_prime: primes endpoint (execute without interruption)
  397. * @num: endpoint number
  398. * @dir: endpoint direction
  399. * @is_ctrl: true if control endpoint
  400. *
  401. * This function returns an error code
  402. */
  403. static int hw_ep_prime(int num, int dir, int is_ctrl)
  404. {
  405. int n = hw_ep_bit(num, dir);
  406. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  407. return -EAGAIN;
  408. hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
  409. while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  410. cpu_relax();
  411. if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
  412. return -EAGAIN;
  413. /* status shoult be tested according with manual but it doesn't work */
  414. return 0;
  415. }
  416. /**
  417. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  418. * without interruption)
  419. * @num: endpoint number
  420. * @dir: endpoint direction
  421. * @value: true => stall, false => unstall
  422. *
  423. * This function returns an error code
  424. */
  425. static int hw_ep_set_halt(int num, int dir, int value)
  426. {
  427. if (value != 0 && value != 1)
  428. return -EINVAL;
  429. do {
  430. u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
  431. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  432. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  433. /* data toggle - reserved for EP0 but it's in ESS */
  434. hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
  435. } while (value != hw_ep_get_halt(num, dir));
  436. return 0;
  437. }
  438. /**
  439. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  440. * interruption)
  441. * @n: interrupt bit
  442. *
  443. * This function returns an error code
  444. */
  445. static int hw_intr_clear(int n)
  446. {
  447. if (n >= REG_BITS)
  448. return -EINVAL;
  449. hw_cwrite(CAP_USBINTR, BIT(n), 0);
  450. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  451. return 0;
  452. }
  453. /**
  454. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  455. * interruption)
  456. * @n: interrupt bit
  457. *
  458. * This function returns an error code
  459. */
  460. static int hw_intr_force(int n)
  461. {
  462. if (n >= REG_BITS)
  463. return -EINVAL;
  464. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  465. hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
  466. hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
  467. hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
  468. return 0;
  469. }
  470. /**
  471. * hw_is_port_high_speed: test if port is high speed
  472. *
  473. * This function returns true if high speed port
  474. */
  475. static int hw_port_is_high_speed(void)
  476. {
  477. return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
  478. hw_cread(CAP_PORTSC, PORTSC_HSP);
  479. }
  480. /**
  481. * hw_port_test_get: reads port test mode value
  482. *
  483. * This function returns port test mode value
  484. */
  485. static u8 hw_port_test_get(void)
  486. {
  487. return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  488. }
  489. /**
  490. * hw_port_test_set: writes port test mode (execute without interruption)
  491. * @mode: new value
  492. *
  493. * This function returns an error code
  494. */
  495. static int hw_port_test_set(u8 mode)
  496. {
  497. const u8 TEST_MODE_MAX = 7;
  498. if (mode > TEST_MODE_MAX)
  499. return -EINVAL;
  500. hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  501. return 0;
  502. }
  503. /**
  504. * hw_read_intr_enable: returns interrupt enable register
  505. *
  506. * This function returns register data
  507. */
  508. static u32 hw_read_intr_enable(void)
  509. {
  510. return hw_cread(CAP_USBINTR, ~0);
  511. }
  512. /**
  513. * hw_read_intr_status: returns interrupt status register
  514. *
  515. * This function returns register data
  516. */
  517. static u32 hw_read_intr_status(void)
  518. {
  519. return hw_cread(CAP_USBSTS, ~0);
  520. }
  521. /**
  522. * hw_register_read: reads all device registers (execute without interruption)
  523. * @buf: destination buffer
  524. * @size: buffer size
  525. *
  526. * This function returns number of registers read
  527. */
  528. static size_t hw_register_read(u32 *buf, size_t size)
  529. {
  530. unsigned i;
  531. if (size > hw_bank.size)
  532. size = hw_bank.size;
  533. for (i = 0; i < size; i++)
  534. buf[i] = hw_aread(i * sizeof(u32), ~0);
  535. return size;
  536. }
  537. /**
  538. * hw_register_write: writes to register
  539. * @addr: register address
  540. * @data: register value
  541. *
  542. * This function returns an error code
  543. */
  544. static int hw_register_write(u16 addr, u32 data)
  545. {
  546. /* align */
  547. addr /= sizeof(u32);
  548. if (addr >= hw_bank.size)
  549. return -EINVAL;
  550. /* align */
  551. addr *= sizeof(u32);
  552. hw_awrite(addr, ~0, data);
  553. return 0;
  554. }
  555. /**
  556. * hw_test_and_clear_complete: test & clear complete status (execute without
  557. * interruption)
  558. * @n: bit number (endpoint)
  559. *
  560. * This function returns complete status
  561. */
  562. static int hw_test_and_clear_complete(int n)
  563. {
  564. return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
  565. }
  566. /**
  567. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  568. * without interruption)
  569. *
  570. * This function returns active interrutps
  571. */
  572. static u32 hw_test_and_clear_intr_active(void)
  573. {
  574. u32 reg = hw_read_intr_status() & hw_read_intr_enable();
  575. hw_cwrite(CAP_USBSTS, ~0, reg);
  576. return reg;
  577. }
  578. /**
  579. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  580. * interruption)
  581. *
  582. * This function returns guard value
  583. */
  584. static int hw_test_and_clear_setup_guard(void)
  585. {
  586. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
  587. }
  588. /**
  589. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  590. * interruption)
  591. *
  592. * This function returns guard value
  593. */
  594. static int hw_test_and_set_setup_guard(void)
  595. {
  596. return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  597. }
  598. /**
  599. * hw_usb_set_address: configures USB address (execute without interruption)
  600. * @value: new USB address
  601. *
  602. * This function returns an error code
  603. */
  604. static int hw_usb_set_address(u8 value)
  605. {
  606. /* advance */
  607. hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  608. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  609. return 0;
  610. }
  611. /**
  612. * hw_usb_reset: restart device after a bus reset (execute without
  613. * interruption)
  614. *
  615. * This function returns an error code
  616. */
  617. static int hw_usb_reset(void)
  618. {
  619. hw_usb_set_address(0);
  620. /* ESS flushes only at end?!? */
  621. hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
  622. /* clear setup token semaphores */
  623. hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
  624. /* clear complete status */
  625. hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
  626. /* wait until all bits cleared */
  627. while (hw_cread(CAP_ENDPTPRIME, ~0))
  628. udelay(10); /* not RTOS friendly */
  629. /* reset all endpoints ? */
  630. /* reset internal status and wait for further instructions
  631. no need to verify the port reset status (ESS does it) */
  632. return 0;
  633. }
  634. /******************************************************************************
  635. * DBG block
  636. *****************************************************************************/
  637. /**
  638. * show_device: prints information about device capabilities and status
  639. *
  640. * Check "device.h" for details
  641. */
  642. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  643. char *buf)
  644. {
  645. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  646. struct usb_gadget *gadget = &udc->gadget;
  647. int n = 0;
  648. dbg_trace("[%s] %p\n", __func__, buf);
  649. if (attr == NULL || buf == NULL) {
  650. dev_err(dev, "[%s] EINVAL\n", __func__);
  651. return 0;
  652. }
  653. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  654. gadget->speed);
  655. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  656. gadget->is_dualspeed);
  657. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  658. gadget->is_otg);
  659. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  660. gadget->is_a_peripheral);
  661. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  662. gadget->b_hnp_enable);
  663. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  664. gadget->a_hnp_support);
  665. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  666. gadget->a_alt_hnp_support);
  667. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  668. (gadget->name ? gadget->name : ""));
  669. return n;
  670. }
  671. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  672. /**
  673. * show_driver: prints information about attached gadget (if any)
  674. *
  675. * Check "device.h" for details
  676. */
  677. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  678. char *buf)
  679. {
  680. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  681. struct usb_gadget_driver *driver = udc->driver;
  682. int n = 0;
  683. dbg_trace("[%s] %p\n", __func__, buf);
  684. if (attr == NULL || buf == NULL) {
  685. dev_err(dev, "[%s] EINVAL\n", __func__);
  686. return 0;
  687. }
  688. if (driver == NULL)
  689. return scnprintf(buf, PAGE_SIZE,
  690. "There is no gadget attached!\n");
  691. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  692. (driver->function ? driver->function : ""));
  693. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  694. driver->speed);
  695. return n;
  696. }
  697. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  698. /* Maximum event message length */
  699. #define DBG_DATA_MSG 64UL
  700. /* Maximum event messages */
  701. #define DBG_DATA_MAX 128UL
  702. /* Event buffer descriptor */
  703. static struct {
  704. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  705. unsigned idx; /* index */
  706. unsigned tty; /* print to console? */
  707. rwlock_t lck; /* lock */
  708. } dbg_data = {
  709. .idx = 0,
  710. .tty = 0,
  711. .lck = __RW_LOCK_UNLOCKED(lck)
  712. };
  713. /**
  714. * dbg_dec: decrements debug event index
  715. * @idx: buffer index
  716. */
  717. static void dbg_dec(unsigned *idx)
  718. {
  719. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  720. }
  721. /**
  722. * dbg_inc: increments debug event index
  723. * @idx: buffer index
  724. */
  725. static void dbg_inc(unsigned *idx)
  726. {
  727. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  728. }
  729. /**
  730. * dbg_print: prints the common part of the event
  731. * @addr: endpoint address
  732. * @name: event name
  733. * @status: status
  734. * @extra: extra information
  735. */
  736. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  737. {
  738. struct timeval tval;
  739. unsigned int stamp;
  740. unsigned long flags;
  741. write_lock_irqsave(&dbg_data.lck, flags);
  742. do_gettimeofday(&tval);
  743. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  744. stamp = stamp * 1000000 + tval.tv_usec;
  745. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  746. "%04X\t» %02X %-7.7s %4i «\t%s\n",
  747. stamp, addr, name, status, extra);
  748. dbg_inc(&dbg_data.idx);
  749. write_unlock_irqrestore(&dbg_data.lck, flags);
  750. if (dbg_data.tty != 0)
  751. pr_notice("%04X\t» %02X %-7.7s %4i «\t%s\n",
  752. stamp, addr, name, status, extra);
  753. }
  754. /**
  755. * dbg_done: prints a DONE event
  756. * @addr: endpoint address
  757. * @td: transfer descriptor
  758. * @status: status
  759. */
  760. static void dbg_done(u8 addr, const u32 token, int status)
  761. {
  762. char msg[DBG_DATA_MSG];
  763. scnprintf(msg, sizeof(msg), "%d %02X",
  764. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  765. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  766. dbg_print(addr, "DONE", status, msg);
  767. }
  768. /**
  769. * dbg_event: prints a generic event
  770. * @addr: endpoint address
  771. * @name: event name
  772. * @status: status
  773. */
  774. static void dbg_event(u8 addr, const char *name, int status)
  775. {
  776. if (name != NULL)
  777. dbg_print(addr, name, status, "");
  778. }
  779. /*
  780. * dbg_queue: prints a QUEUE event
  781. * @addr: endpoint address
  782. * @req: USB request
  783. * @status: status
  784. */
  785. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  786. {
  787. char msg[DBG_DATA_MSG];
  788. if (req != NULL) {
  789. scnprintf(msg, sizeof(msg),
  790. "%d %d", !req->no_interrupt, req->length);
  791. dbg_print(addr, "QUEUE", status, msg);
  792. }
  793. }
  794. /**
  795. * dbg_setup: prints a SETUP event
  796. * @addr: endpoint address
  797. * @req: setup request
  798. */
  799. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  800. {
  801. char msg[DBG_DATA_MSG];
  802. if (req != NULL) {
  803. scnprintf(msg, sizeof(msg),
  804. "%02X %02X %04X %04X %d", req->bRequestType,
  805. req->bRequest, le16_to_cpu(req->wValue),
  806. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  807. dbg_print(addr, "SETUP", 0, msg);
  808. }
  809. }
  810. /**
  811. * show_events: displays the event buffer
  812. *
  813. * Check "device.h" for details
  814. */
  815. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  816. char *buf)
  817. {
  818. unsigned long flags;
  819. unsigned i, j, n = 0;
  820. dbg_trace("[%s] %p\n", __func__, buf);
  821. if (attr == NULL || buf == NULL) {
  822. dev_err(dev, "[%s] EINVAL\n", __func__);
  823. return 0;
  824. }
  825. read_lock_irqsave(&dbg_data.lck, flags);
  826. i = dbg_data.idx;
  827. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  828. n += strlen(dbg_data.buf[i]);
  829. if (n >= PAGE_SIZE) {
  830. n -= strlen(dbg_data.buf[i]);
  831. break;
  832. }
  833. }
  834. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  835. j += scnprintf(buf + j, PAGE_SIZE - j,
  836. "%s", dbg_data.buf[i]);
  837. read_unlock_irqrestore(&dbg_data.lck, flags);
  838. return n;
  839. }
  840. /**
  841. * store_events: configure if events are going to be also printed to console
  842. *
  843. * Check "device.h" for details
  844. */
  845. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  846. const char *buf, size_t count)
  847. {
  848. unsigned tty;
  849. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  850. if (attr == NULL || buf == NULL) {
  851. dev_err(dev, "[%s] EINVAL\n", __func__);
  852. goto done;
  853. }
  854. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  855. dev_err(dev, "<1|0>: enable|disable console log\n");
  856. goto done;
  857. }
  858. dbg_data.tty = tty;
  859. dev_info(dev, "tty = %u", dbg_data.tty);
  860. done:
  861. return count;
  862. }
  863. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  864. /**
  865. * show_inters: interrupt status, enable status and historic
  866. *
  867. * Check "device.h" for details
  868. */
  869. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  870. char *buf)
  871. {
  872. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  873. unsigned long flags;
  874. u32 intr;
  875. unsigned i, j, n = 0;
  876. dbg_trace("[%s] %p\n", __func__, buf);
  877. if (attr == NULL || buf == NULL) {
  878. dev_err(dev, "[%s] EINVAL\n", __func__);
  879. return 0;
  880. }
  881. spin_lock_irqsave(udc->lock, flags);
  882. n += scnprintf(buf + n, PAGE_SIZE - n,
  883. "status = %08x\n", hw_read_intr_status());
  884. n += scnprintf(buf + n, PAGE_SIZE - n,
  885. "enable = %08x\n", hw_read_intr_enable());
  886. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  887. isr_statistics.test);
  888. n += scnprintf(buf + n, PAGE_SIZE - n, "» ui = %d\n",
  889. isr_statistics.ui);
  890. n += scnprintf(buf + n, PAGE_SIZE - n, "» uei = %d\n",
  891. isr_statistics.uei);
  892. n += scnprintf(buf + n, PAGE_SIZE - n, "» pci = %d\n",
  893. isr_statistics.pci);
  894. n += scnprintf(buf + n, PAGE_SIZE - n, "» uri = %d\n",
  895. isr_statistics.uri);
  896. n += scnprintf(buf + n, PAGE_SIZE - n, "» sli = %d\n",
  897. isr_statistics.sli);
  898. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  899. isr_statistics.none);
  900. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  901. isr_statistics.hndl.cnt);
  902. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  903. i &= ISR_MASK;
  904. intr = isr_statistics.hndl.buf[i];
  905. if (USBi_UI & intr)
  906. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  907. intr &= ~USBi_UI;
  908. if (USBi_UEI & intr)
  909. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  910. intr &= ~USBi_UEI;
  911. if (USBi_PCI & intr)
  912. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  913. intr &= ~USBi_PCI;
  914. if (USBi_URI & intr)
  915. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  916. intr &= ~USBi_URI;
  917. if (USBi_SLI & intr)
  918. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  919. intr &= ~USBi_SLI;
  920. if (intr)
  921. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  922. if (isr_statistics.hndl.buf[i])
  923. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  924. }
  925. spin_unlock_irqrestore(udc->lock, flags);
  926. return n;
  927. }
  928. /**
  929. * store_inters: enable & force or disable an individual interrutps
  930. * (to be used for test purposes only)
  931. *
  932. * Check "device.h" for details
  933. */
  934. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  935. const char *buf, size_t count)
  936. {
  937. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  938. unsigned long flags;
  939. unsigned en, bit;
  940. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  941. if (attr == NULL || buf == NULL) {
  942. dev_err(dev, "[%s] EINVAL\n", __func__);
  943. goto done;
  944. }
  945. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  946. dev_err(dev, "<1|0> <bit>: enable|disable interrupt");
  947. goto done;
  948. }
  949. spin_lock_irqsave(udc->lock, flags);
  950. if (en) {
  951. if (hw_intr_force(bit))
  952. dev_err(dev, "invalid bit number\n");
  953. else
  954. isr_statistics.test++;
  955. } else {
  956. if (hw_intr_clear(bit))
  957. dev_err(dev, "invalid bit number\n");
  958. }
  959. spin_unlock_irqrestore(udc->lock, flags);
  960. done:
  961. return count;
  962. }
  963. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  964. /**
  965. * show_port_test: reads port test mode
  966. *
  967. * Check "device.h" for details
  968. */
  969. static ssize_t show_port_test(struct device *dev,
  970. struct device_attribute *attr, char *buf)
  971. {
  972. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  973. unsigned long flags;
  974. unsigned mode;
  975. dbg_trace("[%s] %p\n", __func__, buf);
  976. if (attr == NULL || buf == NULL) {
  977. dev_err(dev, "[%s] EINVAL\n", __func__);
  978. return 0;
  979. }
  980. spin_lock_irqsave(udc->lock, flags);
  981. mode = hw_port_test_get();
  982. spin_unlock_irqrestore(udc->lock, flags);
  983. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  984. }
  985. /**
  986. * store_port_test: writes port test mode
  987. *
  988. * Check "device.h" for details
  989. */
  990. static ssize_t store_port_test(struct device *dev,
  991. struct device_attribute *attr,
  992. const char *buf, size_t count)
  993. {
  994. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  995. unsigned long flags;
  996. unsigned mode;
  997. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  998. if (attr == NULL || buf == NULL) {
  999. dev_err(dev, "[%s] EINVAL\n", __func__);
  1000. goto done;
  1001. }
  1002. if (sscanf(buf, "%u", &mode) != 1) {
  1003. dev_err(dev, "<mode>: set port test mode");
  1004. goto done;
  1005. }
  1006. spin_lock_irqsave(udc->lock, flags);
  1007. if (hw_port_test_set(mode))
  1008. dev_err(dev, "invalid mode\n");
  1009. spin_unlock_irqrestore(udc->lock, flags);
  1010. done:
  1011. return count;
  1012. }
  1013. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1014. show_port_test, store_port_test);
  1015. /**
  1016. * show_qheads: DMA contents of all queue heads
  1017. *
  1018. * Check "device.h" for details
  1019. */
  1020. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1021. char *buf)
  1022. {
  1023. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1024. unsigned long flags;
  1025. unsigned i, j, n = 0;
  1026. dbg_trace("[%s] %p\n", __func__, buf);
  1027. if (attr == NULL || buf == NULL) {
  1028. dev_err(dev, "[%s] EINVAL\n", __func__);
  1029. return 0;
  1030. }
  1031. spin_lock_irqsave(udc->lock, flags);
  1032. for (i = 0; i < hw_ep_max/2; i++) {
  1033. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1034. struct ci13xxx_ep *mEpTx = &udc->ci13xxx_ep[i + hw_ep_max/2];
  1035. n += scnprintf(buf + n, PAGE_SIZE - n,
  1036. "EP=%02i: RX=%08X TX=%08X\n",
  1037. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1038. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1039. n += scnprintf(buf + n, PAGE_SIZE - n,
  1040. " %04X: %08X %08X\n", j,
  1041. *((u32 *)mEpRx->qh.ptr + j),
  1042. *((u32 *)mEpTx->qh.ptr + j));
  1043. }
  1044. }
  1045. spin_unlock_irqrestore(udc->lock, flags);
  1046. return n;
  1047. }
  1048. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1049. /**
  1050. * show_registers: dumps all registers
  1051. *
  1052. * Check "device.h" for details
  1053. */
  1054. static ssize_t show_registers(struct device *dev,
  1055. struct device_attribute *attr, char *buf)
  1056. {
  1057. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1058. unsigned long flags;
  1059. u32 dump[512];
  1060. unsigned i, k, n = 0;
  1061. dbg_trace("[%s] %p\n", __func__, buf);
  1062. if (attr == NULL || buf == NULL) {
  1063. dev_err(dev, "[%s] EINVAL\n", __func__);
  1064. return 0;
  1065. }
  1066. spin_lock_irqsave(udc->lock, flags);
  1067. k = hw_register_read(dump, sizeof(dump)/sizeof(u32));
  1068. spin_unlock_irqrestore(udc->lock, flags);
  1069. for (i = 0; i < k; i++) {
  1070. n += scnprintf(buf + n, PAGE_SIZE - n,
  1071. "reg[0x%04X] = 0x%08X\n",
  1072. i * (unsigned)sizeof(u32), dump[i]);
  1073. }
  1074. return n;
  1075. }
  1076. /**
  1077. * store_registers: writes value to register address
  1078. *
  1079. * Check "device.h" for details
  1080. */
  1081. static ssize_t store_registers(struct device *dev,
  1082. struct device_attribute *attr,
  1083. const char *buf, size_t count)
  1084. {
  1085. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1086. unsigned long addr, data, flags;
  1087. dbg_trace("[%s] %p, %d\n", __func__, buf, count);
  1088. if (attr == NULL || buf == NULL) {
  1089. dev_err(dev, "[%s] EINVAL\n", __func__);
  1090. goto done;
  1091. }
  1092. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1093. dev_err(dev, "<addr> <data>: write data to register address");
  1094. goto done;
  1095. }
  1096. spin_lock_irqsave(udc->lock, flags);
  1097. if (hw_register_write(addr, data))
  1098. dev_err(dev, "invalid address range\n");
  1099. spin_unlock_irqrestore(udc->lock, flags);
  1100. done:
  1101. return count;
  1102. }
  1103. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1104. show_registers, store_registers);
  1105. /**
  1106. * show_requests: DMA contents of all requests currently queued (all endpts)
  1107. *
  1108. * Check "device.h" for details
  1109. */
  1110. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1111. char *buf)
  1112. {
  1113. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1114. unsigned long flags;
  1115. struct list_head *ptr = NULL;
  1116. struct ci13xxx_req *req = NULL;
  1117. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1118. dbg_trace("[%s] %p\n", __func__, buf);
  1119. if (attr == NULL || buf == NULL) {
  1120. dev_err(dev, "[%s] EINVAL\n", __func__);
  1121. return 0;
  1122. }
  1123. spin_lock_irqsave(udc->lock, flags);
  1124. for (i = 0; i < hw_ep_max; i++)
  1125. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1126. {
  1127. req = list_entry(ptr, struct ci13xxx_req, queue);
  1128. n += scnprintf(buf + n, PAGE_SIZE - n,
  1129. "EP=%02i: TD=%08X %s\n",
  1130. i % hw_ep_max/2, (u32)req->dma,
  1131. ((i < hw_ep_max/2) ? "RX" : "TX"));
  1132. for (j = 0; j < qSize; j++)
  1133. n += scnprintf(buf + n, PAGE_SIZE - n,
  1134. " %04X: %08X\n", j,
  1135. *((u32 *)req->ptr + j));
  1136. }
  1137. spin_unlock_irqrestore(udc->lock, flags);
  1138. return n;
  1139. }
  1140. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1141. /**
  1142. * dbg_create_files: initializes the attribute interface
  1143. * @dev: device
  1144. *
  1145. * This function returns an error code
  1146. */
  1147. __maybe_unused static int dbg_create_files(struct device *dev)
  1148. {
  1149. int retval = 0;
  1150. if (dev == NULL)
  1151. return -EINVAL;
  1152. retval = device_create_file(dev, &dev_attr_device);
  1153. if (retval)
  1154. goto done;
  1155. retval = device_create_file(dev, &dev_attr_driver);
  1156. if (retval)
  1157. goto rm_device;
  1158. retval = device_create_file(dev, &dev_attr_events);
  1159. if (retval)
  1160. goto rm_driver;
  1161. retval = device_create_file(dev, &dev_attr_inters);
  1162. if (retval)
  1163. goto rm_events;
  1164. retval = device_create_file(dev, &dev_attr_port_test);
  1165. if (retval)
  1166. goto rm_inters;
  1167. retval = device_create_file(dev, &dev_attr_qheads);
  1168. if (retval)
  1169. goto rm_port_test;
  1170. retval = device_create_file(dev, &dev_attr_registers);
  1171. if (retval)
  1172. goto rm_qheads;
  1173. retval = device_create_file(dev, &dev_attr_requests);
  1174. if (retval)
  1175. goto rm_registers;
  1176. return 0;
  1177. rm_registers:
  1178. device_remove_file(dev, &dev_attr_registers);
  1179. rm_qheads:
  1180. device_remove_file(dev, &dev_attr_qheads);
  1181. rm_port_test:
  1182. device_remove_file(dev, &dev_attr_port_test);
  1183. rm_inters:
  1184. device_remove_file(dev, &dev_attr_inters);
  1185. rm_events:
  1186. device_remove_file(dev, &dev_attr_events);
  1187. rm_driver:
  1188. device_remove_file(dev, &dev_attr_driver);
  1189. rm_device:
  1190. device_remove_file(dev, &dev_attr_device);
  1191. done:
  1192. return retval;
  1193. }
  1194. /**
  1195. * dbg_remove_files: destroys the attribute interface
  1196. * @dev: device
  1197. *
  1198. * This function returns an error code
  1199. */
  1200. __maybe_unused static int dbg_remove_files(struct device *dev)
  1201. {
  1202. if (dev == NULL)
  1203. return -EINVAL;
  1204. device_remove_file(dev, &dev_attr_requests);
  1205. device_remove_file(dev, &dev_attr_registers);
  1206. device_remove_file(dev, &dev_attr_qheads);
  1207. device_remove_file(dev, &dev_attr_port_test);
  1208. device_remove_file(dev, &dev_attr_inters);
  1209. device_remove_file(dev, &dev_attr_events);
  1210. device_remove_file(dev, &dev_attr_driver);
  1211. device_remove_file(dev, &dev_attr_device);
  1212. return 0;
  1213. }
  1214. /******************************************************************************
  1215. * UTIL block
  1216. *****************************************************************************/
  1217. /**
  1218. * _usb_addr: calculates endpoint address from direction & number
  1219. * @ep: endpoint
  1220. */
  1221. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1222. {
  1223. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1224. }
  1225. /**
  1226. * _hardware_queue: configures a request at hardware level
  1227. * @gadget: gadget
  1228. * @mEp: endpoint
  1229. *
  1230. * This function returns an error code
  1231. */
  1232. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1233. {
  1234. unsigned i;
  1235. int ret = 0;
  1236. unsigned length = mReq->req.length;
  1237. trace("%p, %p", mEp, mReq);
  1238. /* don't queue twice */
  1239. if (mReq->req.status == -EALREADY)
  1240. return -EALREADY;
  1241. mReq->req.status = -EALREADY;
  1242. if (length && !mReq->req.dma) {
  1243. mReq->req.dma = \
  1244. dma_map_single(mEp->device, mReq->req.buf,
  1245. length, mEp->dir ? DMA_TO_DEVICE :
  1246. DMA_FROM_DEVICE);
  1247. if (mReq->req.dma == 0)
  1248. return -ENOMEM;
  1249. mReq->map = 1;
  1250. }
  1251. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1252. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1253. &mReq->zdma);
  1254. if (mReq->zptr == NULL) {
  1255. if (mReq->map) {
  1256. dma_unmap_single(mEp->device, mReq->req.dma,
  1257. length, mEp->dir ? DMA_TO_DEVICE :
  1258. DMA_FROM_DEVICE);
  1259. mReq->req.dma = 0;
  1260. mReq->map = 0;
  1261. }
  1262. return -ENOMEM;
  1263. }
  1264. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1265. mReq->zptr->next = TD_TERMINATE;
  1266. mReq->zptr->token = TD_STATUS_ACTIVE;
  1267. if (!mReq->req.no_interrupt)
  1268. mReq->zptr->token |= TD_IOC;
  1269. }
  1270. /*
  1271. * TD configuration
  1272. * TODO - handle requests which spawns into several TDs
  1273. */
  1274. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1275. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1276. mReq->ptr->token &= TD_TOTAL_BYTES;
  1277. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1278. if (mReq->zptr) {
  1279. mReq->ptr->next = mReq->zdma;
  1280. } else {
  1281. mReq->ptr->next = TD_TERMINATE;
  1282. if (!mReq->req.no_interrupt)
  1283. mReq->ptr->token |= TD_IOC;
  1284. }
  1285. mReq->ptr->page[0] = mReq->req.dma;
  1286. for (i = 1; i < 5; i++)
  1287. mReq->ptr->page[i] =
  1288. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1289. if (!list_empty(&mEp->qh.queue)) {
  1290. struct ci13xxx_req *mReqPrev;
  1291. int n = hw_ep_bit(mEp->num, mEp->dir);
  1292. int tmp_stat;
  1293. mReqPrev = list_entry(mEp->qh.queue.prev,
  1294. struct ci13xxx_req, queue);
  1295. if (mReqPrev->zptr)
  1296. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1297. else
  1298. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1299. wmb();
  1300. if (hw_cread(CAP_ENDPTPRIME, BIT(n)))
  1301. goto done;
  1302. do {
  1303. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1304. tmp_stat = hw_cread(CAP_ENDPTSTAT, BIT(n));
  1305. } while (!hw_cread(CAP_USBCMD, USBCMD_ATDTW));
  1306. hw_cwrite(CAP_USBCMD, USBCMD_ATDTW, 0);
  1307. if (tmp_stat)
  1308. goto done;
  1309. }
  1310. /* QH configuration */
  1311. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1312. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1313. mEp->qh.ptr->cap |= QH_ZLT;
  1314. wmb(); /* synchronize before ep prime */
  1315. ret = hw_ep_prime(mEp->num, mEp->dir,
  1316. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1317. done:
  1318. return ret;
  1319. }
  1320. /**
  1321. * _hardware_dequeue: handles a request at hardware level
  1322. * @gadget: gadget
  1323. * @mEp: endpoint
  1324. *
  1325. * This function returns an error code
  1326. */
  1327. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1328. {
  1329. trace("%p, %p", mEp, mReq);
  1330. if (mReq->req.status != -EALREADY)
  1331. return -EINVAL;
  1332. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1333. return -EBUSY;
  1334. if (mReq->zptr) {
  1335. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1336. return -EBUSY;
  1337. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1338. mReq->zptr = NULL;
  1339. }
  1340. mReq->req.status = 0;
  1341. if (mReq->map) {
  1342. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1343. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1344. mReq->req.dma = 0;
  1345. mReq->map = 0;
  1346. }
  1347. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1348. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1349. mReq->req.status = -1;
  1350. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1351. mReq->req.status = -1;
  1352. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1353. mReq->req.status = -1;
  1354. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1355. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1356. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1357. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1358. return mReq->req.actual;
  1359. }
  1360. /**
  1361. * _ep_nuke: dequeues all endpoint requests
  1362. * @mEp: endpoint
  1363. *
  1364. * This function returns an error code
  1365. * Caller must hold lock
  1366. */
  1367. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1368. __releases(mEp->lock)
  1369. __acquires(mEp->lock)
  1370. {
  1371. trace("%p", mEp);
  1372. if (mEp == NULL)
  1373. return -EINVAL;
  1374. hw_ep_flush(mEp->num, mEp->dir);
  1375. while (!list_empty(&mEp->qh.queue)) {
  1376. /* pop oldest request */
  1377. struct ci13xxx_req *mReq = \
  1378. list_entry(mEp->qh.queue.next,
  1379. struct ci13xxx_req, queue);
  1380. list_del_init(&mReq->queue);
  1381. mReq->req.status = -ESHUTDOWN;
  1382. if (mReq->req.complete != NULL) {
  1383. spin_unlock(mEp->lock);
  1384. mReq->req.complete(&mEp->ep, &mReq->req);
  1385. spin_lock(mEp->lock);
  1386. }
  1387. }
  1388. return 0;
  1389. }
  1390. /**
  1391. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1392. * @gadget: gadget
  1393. *
  1394. * This function returns an error code
  1395. * Caller must hold lock
  1396. */
  1397. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1398. {
  1399. struct usb_ep *ep;
  1400. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1401. unsigned long flags;
  1402. trace("%p", gadget);
  1403. if (gadget == NULL)
  1404. return -EINVAL;
  1405. spin_lock_irqsave(udc->lock, flags);
  1406. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1407. udc->remote_wakeup = 0;
  1408. udc->suspended = 0;
  1409. spin_unlock_irqrestore(udc->lock, flags);
  1410. /* flush all endpoints */
  1411. gadget_for_each_ep(ep, gadget) {
  1412. usb_ep_fifo_flush(ep);
  1413. }
  1414. usb_ep_fifo_flush(&udc->ep0out.ep);
  1415. usb_ep_fifo_flush(&udc->ep0in.ep);
  1416. udc->driver->disconnect(gadget);
  1417. /* make sure to disable all endpoints */
  1418. gadget_for_each_ep(ep, gadget) {
  1419. usb_ep_disable(ep);
  1420. }
  1421. if (udc->status != NULL) {
  1422. usb_ep_free_request(&udc->ep0in.ep, udc->status);
  1423. udc->status = NULL;
  1424. }
  1425. return 0;
  1426. }
  1427. /******************************************************************************
  1428. * ISR block
  1429. *****************************************************************************/
  1430. /**
  1431. * isr_reset_handler: USB reset interrupt handler
  1432. * @udc: UDC device
  1433. *
  1434. * This function resets USB engine after a bus reset occurred
  1435. */
  1436. static void isr_reset_handler(struct ci13xxx *udc)
  1437. __releases(udc->lock)
  1438. __acquires(udc->lock)
  1439. {
  1440. int retval;
  1441. trace("%p", udc);
  1442. if (udc == NULL) {
  1443. err("EINVAL");
  1444. return;
  1445. }
  1446. dbg_event(0xFF, "BUS RST", 0);
  1447. spin_unlock(udc->lock);
  1448. retval = _gadget_stop_activity(&udc->gadget);
  1449. if (retval)
  1450. goto done;
  1451. retval = hw_usb_reset();
  1452. if (retval)
  1453. goto done;
  1454. udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
  1455. if (udc->status == NULL)
  1456. retval = -ENOMEM;
  1457. spin_lock(udc->lock);
  1458. done:
  1459. if (retval)
  1460. err("error: %i", retval);
  1461. }
  1462. /**
  1463. * isr_get_status_complete: get_status request complete function
  1464. * @ep: endpoint
  1465. * @req: request handled
  1466. *
  1467. * Caller must release lock
  1468. */
  1469. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1470. {
  1471. trace("%p, %p", ep, req);
  1472. if (ep == NULL || req == NULL) {
  1473. err("EINVAL");
  1474. return;
  1475. }
  1476. kfree(req->buf);
  1477. usb_ep_free_request(ep, req);
  1478. }
  1479. /**
  1480. * isr_get_status_response: get_status request response
  1481. * @udc: udc struct
  1482. * @setup: setup request packet
  1483. *
  1484. * This function returns an error code
  1485. */
  1486. static int isr_get_status_response(struct ci13xxx *udc,
  1487. struct usb_ctrlrequest *setup)
  1488. __releases(mEp->lock)
  1489. __acquires(mEp->lock)
  1490. {
  1491. struct ci13xxx_ep *mEp = &udc->ep0in;
  1492. struct usb_request *req = NULL;
  1493. gfp_t gfp_flags = GFP_ATOMIC;
  1494. int dir, num, retval;
  1495. trace("%p, %p", mEp, setup);
  1496. if (mEp == NULL || setup == NULL)
  1497. return -EINVAL;
  1498. spin_unlock(mEp->lock);
  1499. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1500. spin_lock(mEp->lock);
  1501. if (req == NULL)
  1502. return -ENOMEM;
  1503. req->complete = isr_get_status_complete;
  1504. req->length = 2;
  1505. req->buf = kzalloc(req->length, gfp_flags);
  1506. if (req->buf == NULL) {
  1507. retval = -ENOMEM;
  1508. goto err_free_req;
  1509. }
  1510. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1511. /* Assume that device is bus powered for now. */
  1512. *((u16 *)req->buf) = _udc->remote_wakeup << 1;
  1513. retval = 0;
  1514. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1515. == USB_RECIP_ENDPOINT) {
  1516. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1517. TX : RX;
  1518. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1519. *((u16 *)req->buf) = hw_ep_get_halt(num, dir);
  1520. }
  1521. /* else do nothing; reserved for future use */
  1522. spin_unlock(mEp->lock);
  1523. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1524. spin_lock(mEp->lock);
  1525. if (retval)
  1526. goto err_free_buf;
  1527. return 0;
  1528. err_free_buf:
  1529. kfree(req->buf);
  1530. err_free_req:
  1531. spin_unlock(mEp->lock);
  1532. usb_ep_free_request(&mEp->ep, req);
  1533. spin_lock(mEp->lock);
  1534. return retval;
  1535. }
  1536. /**
  1537. * isr_setup_status_complete: setup_status request complete function
  1538. * @ep: endpoint
  1539. * @req: request handled
  1540. *
  1541. * Caller must release lock. Put the port in test mode if test mode
  1542. * feature is selected.
  1543. */
  1544. static void
  1545. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1546. {
  1547. struct ci13xxx *udc = req->context;
  1548. unsigned long flags;
  1549. trace("%p, %p", ep, req);
  1550. spin_lock_irqsave(udc->lock, flags);
  1551. if (udc->test_mode)
  1552. hw_port_test_set(udc->test_mode);
  1553. spin_unlock_irqrestore(udc->lock, flags);
  1554. }
  1555. /**
  1556. * isr_setup_status_phase: queues the status phase of a setup transation
  1557. * @udc: udc struct
  1558. *
  1559. * This function returns an error code
  1560. */
  1561. static int isr_setup_status_phase(struct ci13xxx *udc)
  1562. __releases(mEp->lock)
  1563. __acquires(mEp->lock)
  1564. {
  1565. int retval;
  1566. struct ci13xxx_ep *mEp;
  1567. trace("%p", udc);
  1568. mEp = (udc->ep0_dir == TX) ? &udc->ep0out : &udc->ep0in;
  1569. udc->status->context = udc;
  1570. udc->status->complete = isr_setup_status_complete;
  1571. spin_unlock(mEp->lock);
  1572. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1573. spin_lock(mEp->lock);
  1574. return retval;
  1575. }
  1576. /**
  1577. * isr_tr_complete_low: transaction complete low level handler
  1578. * @mEp: endpoint
  1579. *
  1580. * This function returns an error code
  1581. * Caller must hold lock
  1582. */
  1583. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1584. __releases(mEp->lock)
  1585. __acquires(mEp->lock)
  1586. {
  1587. struct ci13xxx_req *mReq, *mReqTemp;
  1588. struct ci13xxx_ep *mEpTemp = mEp;
  1589. int uninitialized_var(retval);
  1590. trace("%p", mEp);
  1591. if (list_empty(&mEp->qh.queue))
  1592. return -EINVAL;
  1593. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1594. queue) {
  1595. retval = _hardware_dequeue(mEp, mReq);
  1596. if (retval < 0)
  1597. break;
  1598. list_del_init(&mReq->queue);
  1599. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1600. if (mReq->req.complete != NULL) {
  1601. spin_unlock(mEp->lock);
  1602. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1603. mReq->req.length)
  1604. mEpTemp = &_udc->ep0in;
  1605. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1606. spin_lock(mEp->lock);
  1607. }
  1608. }
  1609. if (retval == -EBUSY)
  1610. retval = 0;
  1611. if (retval < 0)
  1612. dbg_event(_usb_addr(mEp), "DONE", retval);
  1613. return retval;
  1614. }
  1615. /**
  1616. * isr_tr_complete_handler: transaction complete interrupt handler
  1617. * @udc: UDC descriptor
  1618. *
  1619. * This function handles traffic events
  1620. */
  1621. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1622. __releases(udc->lock)
  1623. __acquires(udc->lock)
  1624. {
  1625. unsigned i;
  1626. u8 tmode = 0;
  1627. trace("%p", udc);
  1628. if (udc == NULL) {
  1629. err("EINVAL");
  1630. return;
  1631. }
  1632. for (i = 0; i < hw_ep_max; i++) {
  1633. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1634. int type, num, dir, err = -EINVAL;
  1635. struct usb_ctrlrequest req;
  1636. if (mEp->desc == NULL)
  1637. continue; /* not configured */
  1638. if (hw_test_and_clear_complete(i)) {
  1639. err = isr_tr_complete_low(mEp);
  1640. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1641. if (err > 0) /* needs status phase */
  1642. err = isr_setup_status_phase(udc);
  1643. if (err < 0) {
  1644. dbg_event(_usb_addr(mEp),
  1645. "ERROR", err);
  1646. spin_unlock(udc->lock);
  1647. if (usb_ep_set_halt(&mEp->ep))
  1648. err("error: ep_set_halt");
  1649. spin_lock(udc->lock);
  1650. }
  1651. }
  1652. }
  1653. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1654. !hw_test_and_clear_setup_status(i))
  1655. continue;
  1656. if (i != 0) {
  1657. warn("ctrl traffic received at endpoint");
  1658. continue;
  1659. }
  1660. /*
  1661. * Flush data and handshake transactions of previous
  1662. * setup packet.
  1663. */
  1664. _ep_nuke(&udc->ep0out);
  1665. _ep_nuke(&udc->ep0in);
  1666. /* read_setup_packet */
  1667. do {
  1668. hw_test_and_set_setup_guard();
  1669. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1670. } while (!hw_test_and_clear_setup_guard());
  1671. type = req.bRequestType;
  1672. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1673. dbg_setup(_usb_addr(mEp), &req);
  1674. switch (req.bRequest) {
  1675. case USB_REQ_CLEAR_FEATURE:
  1676. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1677. le16_to_cpu(req.wValue) ==
  1678. USB_ENDPOINT_HALT) {
  1679. if (req.wLength != 0)
  1680. break;
  1681. num = le16_to_cpu(req.wIndex);
  1682. dir = num & USB_ENDPOINT_DIR_MASK;
  1683. num &= USB_ENDPOINT_NUMBER_MASK;
  1684. if (dir) /* TX */
  1685. num += hw_ep_max/2;
  1686. if (!udc->ci13xxx_ep[num].wedge) {
  1687. spin_unlock(udc->lock);
  1688. err = usb_ep_clear_halt(
  1689. &udc->ci13xxx_ep[num].ep);
  1690. spin_lock(udc->lock);
  1691. if (err)
  1692. break;
  1693. }
  1694. err = isr_setup_status_phase(udc);
  1695. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1696. le16_to_cpu(req.wValue) ==
  1697. USB_DEVICE_REMOTE_WAKEUP) {
  1698. if (req.wLength != 0)
  1699. break;
  1700. udc->remote_wakeup = 0;
  1701. err = isr_setup_status_phase(udc);
  1702. } else {
  1703. goto delegate;
  1704. }
  1705. break;
  1706. case USB_REQ_GET_STATUS:
  1707. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1708. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1709. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1710. goto delegate;
  1711. if (le16_to_cpu(req.wLength) != 2 ||
  1712. le16_to_cpu(req.wValue) != 0)
  1713. break;
  1714. err = isr_get_status_response(udc, &req);
  1715. break;
  1716. case USB_REQ_SET_ADDRESS:
  1717. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1718. goto delegate;
  1719. if (le16_to_cpu(req.wLength) != 0 ||
  1720. le16_to_cpu(req.wIndex) != 0)
  1721. break;
  1722. err = hw_usb_set_address((u8)le16_to_cpu(req.wValue));
  1723. if (err)
  1724. break;
  1725. err = isr_setup_status_phase(udc);
  1726. break;
  1727. case USB_REQ_SET_FEATURE:
  1728. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1729. le16_to_cpu(req.wValue) ==
  1730. USB_ENDPOINT_HALT) {
  1731. if (req.wLength != 0)
  1732. break;
  1733. num = le16_to_cpu(req.wIndex);
  1734. dir = num & USB_ENDPOINT_DIR_MASK;
  1735. num &= USB_ENDPOINT_NUMBER_MASK;
  1736. if (dir) /* TX */
  1737. num += hw_ep_max/2;
  1738. spin_unlock(udc->lock);
  1739. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1740. spin_lock(udc->lock);
  1741. if (!err)
  1742. isr_setup_status_phase(udc);
  1743. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1744. if (req.wLength != 0)
  1745. break;
  1746. switch (le16_to_cpu(req.wValue)) {
  1747. case USB_DEVICE_REMOTE_WAKEUP:
  1748. udc->remote_wakeup = 1;
  1749. err = isr_setup_status_phase(udc);
  1750. break;
  1751. case USB_DEVICE_TEST_MODE:
  1752. tmode = le16_to_cpu(req.wIndex) >> 8;
  1753. switch (tmode) {
  1754. case TEST_J:
  1755. case TEST_K:
  1756. case TEST_SE0_NAK:
  1757. case TEST_PACKET:
  1758. case TEST_FORCE_EN:
  1759. udc->test_mode = tmode;
  1760. err = isr_setup_status_phase(
  1761. udc);
  1762. break;
  1763. default:
  1764. break;
  1765. }
  1766. default:
  1767. goto delegate;
  1768. }
  1769. } else {
  1770. goto delegate;
  1771. }
  1772. break;
  1773. default:
  1774. delegate:
  1775. if (req.wLength == 0) /* no data phase */
  1776. udc->ep0_dir = TX;
  1777. spin_unlock(udc->lock);
  1778. err = udc->driver->setup(&udc->gadget, &req);
  1779. spin_lock(udc->lock);
  1780. break;
  1781. }
  1782. if (err < 0) {
  1783. dbg_event(_usb_addr(mEp), "ERROR", err);
  1784. spin_unlock(udc->lock);
  1785. if (usb_ep_set_halt(&mEp->ep))
  1786. err("error: ep_set_halt");
  1787. spin_lock(udc->lock);
  1788. }
  1789. }
  1790. }
  1791. /******************************************************************************
  1792. * ENDPT block
  1793. *****************************************************************************/
  1794. /**
  1795. * ep_enable: configure endpoint, making it usable
  1796. *
  1797. * Check usb_ep_enable() at "usb_gadget.h" for details
  1798. */
  1799. static int ep_enable(struct usb_ep *ep,
  1800. const struct usb_endpoint_descriptor *desc)
  1801. {
  1802. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1803. int retval = 0;
  1804. unsigned long flags;
  1805. trace("%p, %p", ep, desc);
  1806. if (ep == NULL || desc == NULL)
  1807. return -EINVAL;
  1808. spin_lock_irqsave(mEp->lock, flags);
  1809. /* only internal SW should enable ctrl endpts */
  1810. mEp->desc = desc;
  1811. if (!list_empty(&mEp->qh.queue))
  1812. warn("enabling a non-empty endpoint!");
  1813. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1814. mEp->num = usb_endpoint_num(desc);
  1815. mEp->type = usb_endpoint_type(desc);
  1816. mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
  1817. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1818. mEp->qh.ptr->cap = 0;
  1819. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1820. mEp->qh.ptr->cap |= QH_IOS;
  1821. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1822. mEp->qh.ptr->cap &= ~QH_MULT;
  1823. else
  1824. mEp->qh.ptr->cap &= ~QH_ZLT;
  1825. mEp->qh.ptr->cap |=
  1826. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1827. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1828. /*
  1829. * Enable endpoints in the HW other than ep0 as ep0
  1830. * is always enabled
  1831. */
  1832. if (mEp->num)
  1833. retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
  1834. spin_unlock_irqrestore(mEp->lock, flags);
  1835. return retval;
  1836. }
  1837. /**
  1838. * ep_disable: endpoint is no longer usable
  1839. *
  1840. * Check usb_ep_disable() at "usb_gadget.h" for details
  1841. */
  1842. static int ep_disable(struct usb_ep *ep)
  1843. {
  1844. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1845. int direction, retval = 0;
  1846. unsigned long flags;
  1847. trace("%p", ep);
  1848. if (ep == NULL)
  1849. return -EINVAL;
  1850. else if (mEp->desc == NULL)
  1851. return -EBUSY;
  1852. spin_lock_irqsave(mEp->lock, flags);
  1853. /* only internal SW should disable ctrl endpts */
  1854. direction = mEp->dir;
  1855. do {
  1856. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1857. retval |= _ep_nuke(mEp);
  1858. retval |= hw_ep_disable(mEp->num, mEp->dir);
  1859. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1860. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1861. } while (mEp->dir != direction);
  1862. mEp->desc = NULL;
  1863. spin_unlock_irqrestore(mEp->lock, flags);
  1864. return retval;
  1865. }
  1866. /**
  1867. * ep_alloc_request: allocate a request object to use with this endpoint
  1868. *
  1869. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1870. */
  1871. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1872. {
  1873. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1874. struct ci13xxx_req *mReq = NULL;
  1875. trace("%p, %i", ep, gfp_flags);
  1876. if (ep == NULL) {
  1877. err("EINVAL");
  1878. return NULL;
  1879. }
  1880. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1881. if (mReq != NULL) {
  1882. INIT_LIST_HEAD(&mReq->queue);
  1883. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1884. &mReq->dma);
  1885. if (mReq->ptr == NULL) {
  1886. kfree(mReq);
  1887. mReq = NULL;
  1888. }
  1889. }
  1890. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1891. return (mReq == NULL) ? NULL : &mReq->req;
  1892. }
  1893. /**
  1894. * ep_free_request: frees a request object
  1895. *
  1896. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1897. */
  1898. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1899. {
  1900. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1901. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1902. unsigned long flags;
  1903. trace("%p, %p", ep, req);
  1904. if (ep == NULL || req == NULL) {
  1905. err("EINVAL");
  1906. return;
  1907. } else if (!list_empty(&mReq->queue)) {
  1908. err("EBUSY");
  1909. return;
  1910. }
  1911. spin_lock_irqsave(mEp->lock, flags);
  1912. if (mReq->ptr)
  1913. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1914. kfree(mReq);
  1915. dbg_event(_usb_addr(mEp), "FREE", 0);
  1916. spin_unlock_irqrestore(mEp->lock, flags);
  1917. }
  1918. /**
  1919. * ep_queue: queues (submits) an I/O request to an endpoint
  1920. *
  1921. * Check usb_ep_queue()* at usb_gadget.h" for details
  1922. */
  1923. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1924. gfp_t __maybe_unused gfp_flags)
  1925. {
  1926. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1927. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1928. int retval = 0;
  1929. unsigned long flags;
  1930. trace("%p, %p, %X", ep, req, gfp_flags);
  1931. if (ep == NULL || req == NULL || mEp->desc == NULL)
  1932. return -EINVAL;
  1933. spin_lock_irqsave(mEp->lock, flags);
  1934. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1935. if (req->length)
  1936. mEp = (_udc->ep0_dir == RX) ?
  1937. &_udc->ep0out : &_udc->ep0in;
  1938. if (!list_empty(&mEp->qh.queue)) {
  1939. _ep_nuke(mEp);
  1940. retval = -EOVERFLOW;
  1941. warn("endpoint ctrl %X nuked", _usb_addr(mEp));
  1942. }
  1943. }
  1944. /* first nuke then test link, e.g. previous status has not sent */
  1945. if (!list_empty(&mReq->queue)) {
  1946. retval = -EBUSY;
  1947. err("request already in queue");
  1948. goto done;
  1949. }
  1950. if (req->length > (4 * CI13XXX_PAGE_SIZE)) {
  1951. req->length = (4 * CI13XXX_PAGE_SIZE);
  1952. retval = -EMSGSIZE;
  1953. warn("request length truncated");
  1954. }
  1955. dbg_queue(_usb_addr(mEp), req, retval);
  1956. /* push request */
  1957. mReq->req.status = -EINPROGRESS;
  1958. mReq->req.actual = 0;
  1959. retval = _hardware_enqueue(mEp, mReq);
  1960. if (retval == -EALREADY) {
  1961. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1962. retval = 0;
  1963. }
  1964. if (!retval)
  1965. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1966. done:
  1967. spin_unlock_irqrestore(mEp->lock, flags);
  1968. return retval;
  1969. }
  1970. /**
  1971. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1972. *
  1973. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1974. */
  1975. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1976. {
  1977. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1978. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1979. unsigned long flags;
  1980. trace("%p, %p", ep, req);
  1981. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  1982. mEp->desc == NULL || list_empty(&mReq->queue) ||
  1983. list_empty(&mEp->qh.queue))
  1984. return -EINVAL;
  1985. spin_lock_irqsave(mEp->lock, flags);
  1986. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  1987. hw_ep_flush(mEp->num, mEp->dir);
  1988. /* pop request */
  1989. list_del_init(&mReq->queue);
  1990. if (mReq->map) {
  1991. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1992. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1993. mReq->req.dma = 0;
  1994. mReq->map = 0;
  1995. }
  1996. req->status = -ECONNRESET;
  1997. if (mReq->req.complete != NULL) {
  1998. spin_unlock(mEp->lock);
  1999. mReq->req.complete(&mEp->ep, &mReq->req);
  2000. spin_lock(mEp->lock);
  2001. }
  2002. spin_unlock_irqrestore(mEp->lock, flags);
  2003. return 0;
  2004. }
  2005. /**
  2006. * ep_set_halt: sets the endpoint halt feature
  2007. *
  2008. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2009. */
  2010. static int ep_set_halt(struct usb_ep *ep, int value)
  2011. {
  2012. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2013. int direction, retval = 0;
  2014. unsigned long flags;
  2015. trace("%p, %i", ep, value);
  2016. if (ep == NULL || mEp->desc == NULL)
  2017. return -EINVAL;
  2018. spin_lock_irqsave(mEp->lock, flags);
  2019. #ifndef STALL_IN
  2020. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2021. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2022. !list_empty(&mEp->qh.queue)) {
  2023. spin_unlock_irqrestore(mEp->lock, flags);
  2024. return -EAGAIN;
  2025. }
  2026. #endif
  2027. direction = mEp->dir;
  2028. do {
  2029. dbg_event(_usb_addr(mEp), "HALT", value);
  2030. retval |= hw_ep_set_halt(mEp->num, mEp->dir, value);
  2031. if (!value)
  2032. mEp->wedge = 0;
  2033. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2034. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2035. } while (mEp->dir != direction);
  2036. spin_unlock_irqrestore(mEp->lock, flags);
  2037. return retval;
  2038. }
  2039. /**
  2040. * ep_set_wedge: sets the halt feature and ignores clear requests
  2041. *
  2042. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2043. */
  2044. static int ep_set_wedge(struct usb_ep *ep)
  2045. {
  2046. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2047. unsigned long flags;
  2048. trace("%p", ep);
  2049. if (ep == NULL || mEp->desc == NULL)
  2050. return -EINVAL;
  2051. spin_lock_irqsave(mEp->lock, flags);
  2052. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2053. mEp->wedge = 1;
  2054. spin_unlock_irqrestore(mEp->lock, flags);
  2055. return usb_ep_set_halt(ep);
  2056. }
  2057. /**
  2058. * ep_fifo_flush: flushes contents of a fifo
  2059. *
  2060. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2061. */
  2062. static void ep_fifo_flush(struct usb_ep *ep)
  2063. {
  2064. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2065. unsigned long flags;
  2066. trace("%p", ep);
  2067. if (ep == NULL) {
  2068. err("%02X: -EINVAL", _usb_addr(mEp));
  2069. return;
  2070. }
  2071. spin_lock_irqsave(mEp->lock, flags);
  2072. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2073. hw_ep_flush(mEp->num, mEp->dir);
  2074. spin_unlock_irqrestore(mEp->lock, flags);
  2075. }
  2076. /**
  2077. * Endpoint-specific part of the API to the USB controller hardware
  2078. * Check "usb_gadget.h" for details
  2079. */
  2080. static const struct usb_ep_ops usb_ep_ops = {
  2081. .enable = ep_enable,
  2082. .disable = ep_disable,
  2083. .alloc_request = ep_alloc_request,
  2084. .free_request = ep_free_request,
  2085. .queue = ep_queue,
  2086. .dequeue = ep_dequeue,
  2087. .set_halt = ep_set_halt,
  2088. .set_wedge = ep_set_wedge,
  2089. .fifo_flush = ep_fifo_flush,
  2090. };
  2091. /******************************************************************************
  2092. * GADGET block
  2093. *****************************************************************************/
  2094. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2095. {
  2096. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2097. unsigned long flags;
  2098. int gadget_ready = 0;
  2099. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2100. return -EOPNOTSUPP;
  2101. spin_lock_irqsave(udc->lock, flags);
  2102. udc->vbus_active = is_active;
  2103. if (udc->driver)
  2104. gadget_ready = 1;
  2105. spin_unlock_irqrestore(udc->lock, flags);
  2106. if (gadget_ready) {
  2107. if (is_active) {
  2108. pm_runtime_get_sync(&_gadget->dev);
  2109. hw_device_reset(udc);
  2110. hw_device_state(udc->ep0out.qh.dma);
  2111. } else {
  2112. hw_device_state(0);
  2113. if (udc->udc_driver->notify_event)
  2114. udc->udc_driver->notify_event(udc,
  2115. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2116. _gadget_stop_activity(&udc->gadget);
  2117. pm_runtime_put_sync(&_gadget->dev);
  2118. }
  2119. }
  2120. return 0;
  2121. }
  2122. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2123. {
  2124. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2125. unsigned long flags;
  2126. int ret = 0;
  2127. trace();
  2128. spin_lock_irqsave(udc->lock, flags);
  2129. if (!udc->remote_wakeup) {
  2130. ret = -EOPNOTSUPP;
  2131. dbg_trace("remote wakeup feature is not enabled\n");
  2132. goto out;
  2133. }
  2134. if (!hw_cread(CAP_PORTSC, PORTSC_SUSP)) {
  2135. ret = -EINVAL;
  2136. dbg_trace("port is not suspended\n");
  2137. goto out;
  2138. }
  2139. hw_cwrite(CAP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2140. out:
  2141. spin_unlock_irqrestore(udc->lock, flags);
  2142. return ret;
  2143. }
  2144. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2145. {
  2146. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2147. if (udc->transceiver)
  2148. return otg_set_power(udc->transceiver, mA);
  2149. return -ENOTSUPP;
  2150. }
  2151. /**
  2152. * Device operations part of the API to the USB controller hardware,
  2153. * which don't involve endpoints (or i/o)
  2154. * Check "usb_gadget.h" for details
  2155. */
  2156. static const struct usb_gadget_ops usb_gadget_ops = {
  2157. .vbus_session = ci13xxx_vbus_session,
  2158. .wakeup = ci13xxx_wakeup,
  2159. .vbus_draw = ci13xxx_vbus_draw,
  2160. };
  2161. /**
  2162. * usb_gadget_probe_driver: register a gadget driver
  2163. * @driver: the driver being registered
  2164. * @bind: the driver's bind callback
  2165. *
  2166. * Check usb_gadget_probe_driver() at <linux/usb/gadget.h> for details.
  2167. * Interrupts are enabled here.
  2168. */
  2169. int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
  2170. int (*bind)(struct usb_gadget *))
  2171. {
  2172. struct ci13xxx *udc = _udc;
  2173. unsigned long flags;
  2174. int i, j;
  2175. int retval = -ENOMEM;
  2176. trace("%p", driver);
  2177. if (driver == NULL ||
  2178. bind == NULL ||
  2179. driver->setup == NULL ||
  2180. driver->disconnect == NULL ||
  2181. driver->suspend == NULL ||
  2182. driver->resume == NULL)
  2183. return -EINVAL;
  2184. else if (udc == NULL)
  2185. return -ENODEV;
  2186. else if (udc->driver != NULL)
  2187. return -EBUSY;
  2188. /* alloc resources */
  2189. udc->qh_pool = dma_pool_create("ci13xxx_qh", &udc->gadget.dev,
  2190. sizeof(struct ci13xxx_qh),
  2191. 64, CI13XXX_PAGE_SIZE);
  2192. if (udc->qh_pool == NULL)
  2193. return -ENOMEM;
  2194. udc->td_pool = dma_pool_create("ci13xxx_td", &udc->gadget.dev,
  2195. sizeof(struct ci13xxx_td),
  2196. 64, CI13XXX_PAGE_SIZE);
  2197. if (udc->td_pool == NULL) {
  2198. dma_pool_destroy(udc->qh_pool);
  2199. udc->qh_pool = NULL;
  2200. return -ENOMEM;
  2201. }
  2202. spin_lock_irqsave(udc->lock, flags);
  2203. info("hw_ep_max = %d", hw_ep_max);
  2204. udc->gadget.dev.driver = NULL;
  2205. retval = 0;
  2206. for (i = 0; i < hw_ep_max/2; i++) {
  2207. for (j = RX; j <= TX; j++) {
  2208. int k = i + j * hw_ep_max/2;
  2209. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2210. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2211. (j == TX) ? "in" : "out");
  2212. mEp->lock = udc->lock;
  2213. mEp->device = &udc->gadget.dev;
  2214. mEp->td_pool = udc->td_pool;
  2215. mEp->ep.name = mEp->name;
  2216. mEp->ep.ops = &usb_ep_ops;
  2217. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2218. INIT_LIST_HEAD(&mEp->qh.queue);
  2219. spin_unlock_irqrestore(udc->lock, flags);
  2220. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2221. &mEp->qh.dma);
  2222. spin_lock_irqsave(udc->lock, flags);
  2223. if (mEp->qh.ptr == NULL)
  2224. retval = -ENOMEM;
  2225. else
  2226. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2227. /* skip ep0 out and in endpoints */
  2228. if (i == 0)
  2229. continue;
  2230. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2231. }
  2232. }
  2233. if (retval)
  2234. goto done;
  2235. spin_unlock_irqrestore(udc->lock, flags);
  2236. retval = usb_ep_enable(&udc->ep0out.ep, &ctrl_endpt_out_desc);
  2237. if (retval)
  2238. return retval;
  2239. retval = usb_ep_enable(&udc->ep0in.ep, &ctrl_endpt_in_desc);
  2240. if (retval)
  2241. return retval;
  2242. spin_lock_irqsave(udc->lock, flags);
  2243. udc->gadget.ep0 = &udc->ep0in.ep;
  2244. /* bind gadget */
  2245. driver->driver.bus = NULL;
  2246. udc->gadget.dev.driver = &driver->driver;
  2247. spin_unlock_irqrestore(udc->lock, flags);
  2248. retval = bind(&udc->gadget); /* MAY SLEEP */
  2249. spin_lock_irqsave(udc->lock, flags);
  2250. if (retval) {
  2251. udc->gadget.dev.driver = NULL;
  2252. goto done;
  2253. }
  2254. udc->driver = driver;
  2255. pm_runtime_get_sync(&udc->gadget.dev);
  2256. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2257. if (udc->vbus_active) {
  2258. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2259. hw_device_reset(udc);
  2260. } else {
  2261. pm_runtime_put_sync(&udc->gadget.dev);
  2262. goto done;
  2263. }
  2264. }
  2265. retval = hw_device_state(udc->ep0out.qh.dma);
  2266. if (retval)
  2267. pm_runtime_put_sync(&udc->gadget.dev);
  2268. done:
  2269. spin_unlock_irqrestore(udc->lock, flags);
  2270. return retval;
  2271. }
  2272. EXPORT_SYMBOL(usb_gadget_probe_driver);
  2273. /**
  2274. * usb_gadget_unregister_driver: unregister a gadget driver
  2275. *
  2276. * Check usb_gadget_unregister_driver() at "usb_gadget.h" for details
  2277. */
  2278. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  2279. {
  2280. struct ci13xxx *udc = _udc;
  2281. unsigned long i, flags;
  2282. trace("%p", driver);
  2283. if (driver == NULL ||
  2284. driver->unbind == NULL ||
  2285. driver->setup == NULL ||
  2286. driver->disconnect == NULL ||
  2287. driver->suspend == NULL ||
  2288. driver->resume == NULL ||
  2289. driver != udc->driver)
  2290. return -EINVAL;
  2291. spin_lock_irqsave(udc->lock, flags);
  2292. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2293. udc->vbus_active) {
  2294. hw_device_state(0);
  2295. if (udc->udc_driver->notify_event)
  2296. udc->udc_driver->notify_event(udc,
  2297. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2298. _gadget_stop_activity(&udc->gadget);
  2299. pm_runtime_put(&udc->gadget.dev);
  2300. }
  2301. /* unbind gadget */
  2302. spin_unlock_irqrestore(udc->lock, flags);
  2303. driver->unbind(&udc->gadget); /* MAY SLEEP */
  2304. spin_lock_irqsave(udc->lock, flags);
  2305. udc->gadget.dev.driver = NULL;
  2306. /* free resources */
  2307. for (i = 0; i < hw_ep_max; i++) {
  2308. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2309. if (!list_empty(&mEp->ep.ep_list))
  2310. list_del_init(&mEp->ep.ep_list);
  2311. if (mEp->qh.ptr != NULL)
  2312. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2313. }
  2314. udc->gadget.ep0 = NULL;
  2315. udc->driver = NULL;
  2316. spin_unlock_irqrestore(udc->lock, flags);
  2317. if (udc->td_pool != NULL) {
  2318. dma_pool_destroy(udc->td_pool);
  2319. udc->td_pool = NULL;
  2320. }
  2321. if (udc->qh_pool != NULL) {
  2322. dma_pool_destroy(udc->qh_pool);
  2323. udc->qh_pool = NULL;
  2324. }
  2325. return 0;
  2326. }
  2327. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  2328. /******************************************************************************
  2329. * BUS block
  2330. *****************************************************************************/
  2331. /**
  2332. * udc_irq: global interrupt handler
  2333. *
  2334. * This function returns IRQ_HANDLED if the IRQ has been handled
  2335. * It locks access to registers
  2336. */
  2337. static irqreturn_t udc_irq(void)
  2338. {
  2339. struct ci13xxx *udc = _udc;
  2340. irqreturn_t retval;
  2341. u32 intr;
  2342. trace();
  2343. if (udc == NULL) {
  2344. err("ENODEV");
  2345. return IRQ_HANDLED;
  2346. }
  2347. spin_lock(udc->lock);
  2348. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2349. if (hw_cread(CAP_USBMODE, USBMODE_CM) !=
  2350. USBMODE_CM_DEVICE) {
  2351. spin_unlock(udc->lock);
  2352. return IRQ_NONE;
  2353. }
  2354. }
  2355. intr = hw_test_and_clear_intr_active();
  2356. if (intr) {
  2357. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2358. isr_statistics.hndl.idx &= ISR_MASK;
  2359. isr_statistics.hndl.cnt++;
  2360. /* order defines priority - do NOT change it */
  2361. if (USBi_URI & intr) {
  2362. isr_statistics.uri++;
  2363. isr_reset_handler(udc);
  2364. }
  2365. if (USBi_PCI & intr) {
  2366. isr_statistics.pci++;
  2367. udc->gadget.speed = hw_port_is_high_speed() ?
  2368. USB_SPEED_HIGH : USB_SPEED_FULL;
  2369. if (udc->suspended) {
  2370. spin_unlock(udc->lock);
  2371. udc->driver->resume(&udc->gadget);
  2372. spin_lock(udc->lock);
  2373. udc->suspended = 0;
  2374. }
  2375. }
  2376. if (USBi_UEI & intr)
  2377. isr_statistics.uei++;
  2378. if (USBi_UI & intr) {
  2379. isr_statistics.ui++;
  2380. isr_tr_complete_handler(udc);
  2381. }
  2382. if (USBi_SLI & intr) {
  2383. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  2384. udc->suspended = 1;
  2385. spin_unlock(udc->lock);
  2386. udc->driver->suspend(&udc->gadget);
  2387. spin_lock(udc->lock);
  2388. }
  2389. isr_statistics.sli++;
  2390. }
  2391. retval = IRQ_HANDLED;
  2392. } else {
  2393. isr_statistics.none++;
  2394. retval = IRQ_NONE;
  2395. }
  2396. spin_unlock(udc->lock);
  2397. return retval;
  2398. }
  2399. /**
  2400. * udc_release: driver release function
  2401. * @dev: device
  2402. *
  2403. * Currently does nothing
  2404. */
  2405. static void udc_release(struct device *dev)
  2406. {
  2407. trace("%p", dev);
  2408. if (dev == NULL)
  2409. err("EINVAL");
  2410. }
  2411. /**
  2412. * udc_probe: parent probe must call this to initialize UDC
  2413. * @dev: parent device
  2414. * @regs: registers base address
  2415. * @name: driver name
  2416. *
  2417. * This function returns an error code
  2418. * No interrupts active, the IRQ has not been requested yet
  2419. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2420. */
  2421. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2422. void __iomem *regs)
  2423. {
  2424. struct ci13xxx *udc;
  2425. int retval = 0;
  2426. trace("%p, %p, %p", dev, regs, name);
  2427. if (dev == NULL || regs == NULL || driver == NULL ||
  2428. driver->name == NULL)
  2429. return -EINVAL;
  2430. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2431. if (udc == NULL)
  2432. return -ENOMEM;
  2433. udc->lock = &udc_lock;
  2434. udc->regs = regs;
  2435. udc->udc_driver = driver;
  2436. udc->gadget.ops = &usb_gadget_ops;
  2437. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2438. udc->gadget.is_dualspeed = 1;
  2439. udc->gadget.is_otg = 0;
  2440. udc->gadget.name = driver->name;
  2441. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2442. udc->gadget.ep0 = NULL;
  2443. dev_set_name(&udc->gadget.dev, "gadget");
  2444. udc->gadget.dev.dma_mask = dev->dma_mask;
  2445. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2446. udc->gadget.dev.parent = dev;
  2447. udc->gadget.dev.release = udc_release;
  2448. retval = hw_device_init(regs);
  2449. if (retval < 0)
  2450. goto free_udc;
  2451. udc->transceiver = otg_get_transceiver();
  2452. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2453. if (udc->transceiver == NULL) {
  2454. retval = -ENODEV;
  2455. goto free_udc;
  2456. }
  2457. }
  2458. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2459. retval = hw_device_reset(udc);
  2460. if (retval)
  2461. goto put_transceiver;
  2462. }
  2463. retval = device_register(&udc->gadget.dev);
  2464. if (retval) {
  2465. put_device(&udc->gadget.dev);
  2466. goto put_transceiver;
  2467. }
  2468. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2469. retval = dbg_create_files(&udc->gadget.dev);
  2470. #endif
  2471. if (retval)
  2472. goto unreg_device;
  2473. if (udc->transceiver) {
  2474. retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
  2475. if (retval)
  2476. goto remove_dbg;
  2477. }
  2478. pm_runtime_no_callbacks(&udc->gadget.dev);
  2479. pm_runtime_enable(&udc->gadget.dev);
  2480. _udc = udc;
  2481. return retval;
  2482. err("error = %i", retval);
  2483. remove_dbg:
  2484. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2485. dbg_remove_files(&udc->gadget.dev);
  2486. #endif
  2487. unreg_device:
  2488. device_unregister(&udc->gadget.dev);
  2489. put_transceiver:
  2490. if (udc->transceiver)
  2491. otg_put_transceiver(udc->transceiver);
  2492. free_udc:
  2493. kfree(udc);
  2494. _udc = NULL;
  2495. return retval;
  2496. }
  2497. /**
  2498. * udc_remove: parent remove must call this to remove UDC
  2499. *
  2500. * No interrupts active, the IRQ has been released
  2501. */
  2502. static void udc_remove(void)
  2503. {
  2504. struct ci13xxx *udc = _udc;
  2505. if (udc == NULL) {
  2506. err("EINVAL");
  2507. return;
  2508. }
  2509. if (udc->transceiver) {
  2510. otg_set_peripheral(udc->transceiver, &udc->gadget);
  2511. otg_put_transceiver(udc->transceiver);
  2512. }
  2513. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2514. dbg_remove_files(&udc->gadget.dev);
  2515. #endif
  2516. device_unregister(&udc->gadget.dev);
  2517. kfree(udc);
  2518. _udc = NULL;
  2519. }