ql4_mbx.c 36 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine issue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. uint32_t dev_state;
  33. /* Make sure that pointers are valid */
  34. if (!mbx_cmd || !mbx_sts) {
  35. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  36. "pointer\n", ha->host_no, __func__));
  37. return status;
  38. }
  39. if (is_qla8022(ha)) {
  40. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  41. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  42. "prematurely completing mbx cmd as firmware "
  43. "recovery detected\n", ha->host_no, __func__));
  44. return status;
  45. }
  46. /* Do not send any mbx cmd if h/w is in failed state*/
  47. qla4_8xxx_idc_lock(ha);
  48. dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  49. qla4_8xxx_idc_unlock(ha);
  50. if (dev_state == QLA82XX_DEV_FAILED) {
  51. ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: H/W is in "
  52. "failed state, do not send any mailbox commands\n",
  53. ha->host_no, __func__);
  54. return status;
  55. }
  56. }
  57. if ((is_aer_supported(ha)) &&
  58. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  59. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  60. "timeout MBX Exiting.\n", ha->host_no, __func__));
  61. return status;
  62. }
  63. /* Mailbox code active */
  64. wait_count = MBOX_TOV * 100;
  65. while (wait_count--) {
  66. mutex_lock(&ha->mbox_sem);
  67. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  68. set_bit(AF_MBOX_COMMAND, &ha->flags);
  69. mutex_unlock(&ha->mbox_sem);
  70. break;
  71. }
  72. mutex_unlock(&ha->mbox_sem);
  73. if (!wait_count) {
  74. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  75. ha->host_no, __func__));
  76. return status;
  77. }
  78. msleep(10);
  79. }
  80. spin_lock_irqsave(&ha->hardware_lock, flags);
  81. ha->mbox_status_count = outCount;
  82. for (i = 0; i < outCount; i++)
  83. ha->mbox_status[i] = 0;
  84. if (is_qla8022(ha)) {
  85. /* Load all mailbox registers, except mailbox 0. */
  86. DEBUG5(
  87. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  88. for (i = 0; i < inCount; i++)
  89. printk("mb%d=%04x ", i, mbx_cmd[i]);
  90. printk("\n"));
  91. for (i = 1; i < inCount; i++)
  92. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  93. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  94. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  95. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  96. } else {
  97. /* Load all mailbox registers, except mailbox 0. */
  98. for (i = 1; i < inCount; i++)
  99. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  100. /* Wakeup firmware */
  101. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  102. readl(&ha->reg->mailbox[0]);
  103. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  104. readl(&ha->reg->ctrl_status);
  105. }
  106. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  107. /* Wait for completion */
  108. /*
  109. * If we don't want status, don't wait for the mailbox command to
  110. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  111. * you must poll the inbound Interrupt Mask for completion.
  112. */
  113. if (outCount == 0) {
  114. status = QLA_SUCCESS;
  115. goto mbox_exit;
  116. }
  117. /*
  118. * Wait for completion: Poll or completion queue
  119. */
  120. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  121. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  122. test_bit(AF_ONLINE, &ha->flags) &&
  123. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  124. /* Do not poll for completion. Use completion queue */
  125. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  127. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  128. } else {
  129. /* Poll for command to complete */
  130. wait_count = jiffies + MBOX_TOV * HZ;
  131. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  132. if (time_after_eq(jiffies, wait_count))
  133. break;
  134. /*
  135. * Service the interrupt.
  136. * The ISR will save the mailbox status registers
  137. * to a temporary storage location in the adapter
  138. * structure.
  139. */
  140. spin_lock_irqsave(&ha->hardware_lock, flags);
  141. if (is_qla8022(ha)) {
  142. intr_status =
  143. readl(&ha->qla4_8xxx_reg->host_int);
  144. if (intr_status & ISRX_82XX_RISC_INT) {
  145. ha->mbox_status_count = outCount;
  146. intr_status =
  147. readl(&ha->qla4_8xxx_reg->host_status);
  148. ha->isp_ops->interrupt_service_routine(
  149. ha, intr_status);
  150. if (test_bit(AF_INTERRUPTS_ON,
  151. &ha->flags) &&
  152. test_bit(AF_INTx_ENABLED,
  153. &ha->flags))
  154. qla4_8xxx_wr_32(ha,
  155. ha->nx_legacy_intr.tgt_mask_reg,
  156. 0xfbff);
  157. }
  158. } else {
  159. intr_status = readl(&ha->reg->ctrl_status);
  160. if (intr_status & INTR_PENDING) {
  161. /*
  162. * Service the interrupt.
  163. * The ISR will save the mailbox status
  164. * registers to a temporary storage
  165. * location in the adapter structure.
  166. */
  167. ha->mbox_status_count = outCount;
  168. ha->isp_ops->interrupt_service_routine(
  169. ha, intr_status);
  170. }
  171. }
  172. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  173. msleep(10);
  174. }
  175. }
  176. /* Check for mailbox timeout. */
  177. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  178. if (is_qla8022(ha) &&
  179. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  180. DEBUG2(ql4_printk(KERN_INFO, ha,
  181. "scsi%ld: %s: prematurely completing mbx cmd as "
  182. "firmware recovery detected\n",
  183. ha->host_no, __func__));
  184. goto mbox_exit;
  185. }
  186. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  187. " Scheduling Adapter Reset\n", ha->host_no,
  188. mbx_cmd[0]));
  189. ha->mailbox_timeout_count++;
  190. mbx_sts[0] = (-1);
  191. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  192. goto mbox_exit;
  193. }
  194. /*
  195. * Copy the mailbox out registers to the caller's mailbox in/out
  196. * structure.
  197. */
  198. spin_lock_irqsave(&ha->hardware_lock, flags);
  199. for (i = 0; i < outCount; i++)
  200. mbx_sts[i] = ha->mbox_status[i];
  201. /* Set return status and error flags (if applicable). */
  202. switch (ha->mbox_status[0]) {
  203. case MBOX_STS_COMMAND_COMPLETE:
  204. status = QLA_SUCCESS;
  205. break;
  206. case MBOX_STS_INTERMEDIATE_COMPLETION:
  207. status = QLA_SUCCESS;
  208. break;
  209. case MBOX_STS_BUSY:
  210. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  211. ha->host_no, __func__, mbx_cmd[0]));
  212. ha->mailbox_timeout_count++;
  213. break;
  214. default:
  215. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  216. "sts = %08X ****\n", ha->host_no, __func__,
  217. mbx_cmd[0], mbx_sts[0]));
  218. break;
  219. }
  220. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  221. mbox_exit:
  222. mutex_lock(&ha->mbox_sem);
  223. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  224. mutex_unlock(&ha->mbox_sem);
  225. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  226. return status;
  227. }
  228. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  229. {
  230. set_bit(AF_FW_RECOVERY, &ha->flags);
  231. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  232. ha->host_no, __func__);
  233. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  234. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  235. complete(&ha->mbx_intr_comp);
  236. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  237. "recovery, doing premature completion of "
  238. "mbx cmd\n", ha->host_no, __func__);
  239. } else {
  240. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  241. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  242. "recovery, doing premature completion of "
  243. "polling mbx cmd\n", ha->host_no, __func__);
  244. }
  245. }
  246. }
  247. static uint8_t
  248. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  249. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  250. {
  251. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  252. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  253. if (is_qla8022(ha))
  254. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  255. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  256. mbox_cmd[1] = 0;
  257. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  258. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  259. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  260. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  261. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  262. QLA_SUCCESS) {
  263. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  264. "MBOX_CMD_INITIALIZE_FIRMWARE"
  265. " failed w/ status %04X\n",
  266. ha->host_no, __func__, mbox_sts[0]));
  267. return QLA_ERROR;
  268. }
  269. return QLA_SUCCESS;
  270. }
  271. static uint8_t
  272. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  273. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  274. {
  275. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  276. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  277. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  278. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  279. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  280. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  281. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  282. QLA_SUCCESS) {
  283. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  284. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  285. " failed w/ status %04X\n",
  286. ha->host_no, __func__, mbox_sts[0]));
  287. return QLA_ERROR;
  288. }
  289. return QLA_SUCCESS;
  290. }
  291. static void
  292. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  293. struct addr_ctrl_blk *init_fw_cb)
  294. {
  295. /* Save IPv4 Address Info */
  296. memcpy(ha->ip_address, init_fw_cb->ipv4_addr,
  297. min(sizeof(ha->ip_address), sizeof(init_fw_cb->ipv4_addr)));
  298. memcpy(ha->subnet_mask, init_fw_cb->ipv4_subnet,
  299. min(sizeof(ha->subnet_mask), sizeof(init_fw_cb->ipv4_subnet)));
  300. memcpy(ha->gateway, init_fw_cb->ipv4_gw_addr,
  301. min(sizeof(ha->gateway), sizeof(init_fw_cb->ipv4_gw_addr)));
  302. if (is_ipv6_enabled(ha)) {
  303. /* Save IPv6 Address */
  304. ha->ipv6_link_local_state = init_fw_cb->ipv6_lnk_lcl_addr_state;
  305. ha->ipv6_addr0_state = init_fw_cb->ipv6_addr0_state;
  306. ha->ipv6_addr1_state = init_fw_cb->ipv6_addr1_state;
  307. ha->ipv6_default_router_state = init_fw_cb->ipv6_dflt_rtr_state;
  308. ha->ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  309. ha->ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  310. memcpy(&ha->ipv6_link_local_addr.in6_u.u6_addr8[8],
  311. init_fw_cb->ipv6_if_id,
  312. min(sizeof(ha->ipv6_link_local_addr)/2,
  313. sizeof(init_fw_cb->ipv6_if_id)));
  314. memcpy(&ha->ipv6_addr0, init_fw_cb->ipv6_addr0,
  315. min(sizeof(ha->ipv6_addr0),
  316. sizeof(init_fw_cb->ipv6_addr0)));
  317. memcpy(&ha->ipv6_addr1, init_fw_cb->ipv6_addr1,
  318. min(sizeof(ha->ipv6_addr1),
  319. sizeof(init_fw_cb->ipv6_addr1)));
  320. memcpy(&ha->ipv6_default_router_addr,
  321. init_fw_cb->ipv6_dflt_rtr_addr,
  322. min(sizeof(ha->ipv6_default_router_addr),
  323. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  324. }
  325. }
  326. static uint8_t
  327. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  328. uint32_t *mbox_cmd,
  329. uint32_t *mbox_sts,
  330. struct addr_ctrl_blk *init_fw_cb,
  331. dma_addr_t init_fw_cb_dma)
  332. {
  333. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  334. != QLA_SUCCESS) {
  335. DEBUG2(printk(KERN_WARNING
  336. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  337. ha->host_no, __func__));
  338. return QLA_ERROR;
  339. }
  340. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  341. /* Save some info in adapter structure. */
  342. ha->acb_version = init_fw_cb->acb_version;
  343. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  344. ha->tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  345. ha->ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  346. ha->ipv4_addr_state = le16_to_cpu(init_fw_cb->ipv4_addr_state);
  347. ha->heartbeat_interval = init_fw_cb->hb_interval;
  348. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  349. min(sizeof(ha->name_string),
  350. sizeof(init_fw_cb->iscsi_name)));
  351. /*memcpy(ha->alias, init_fw_cb->Alias,
  352. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  353. if (ha->acb_version == ACB_SUPPORTED) {
  354. ha->ipv6_options = init_fw_cb->ipv6_opts;
  355. ha->ipv6_addl_options = init_fw_cb->ipv6_addtl_opts;
  356. }
  357. qla4xxx_update_local_ip(ha, init_fw_cb);
  358. return QLA_SUCCESS;
  359. }
  360. /**
  361. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  362. * @ha: Pointer to host adapter structure.
  363. **/
  364. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  365. {
  366. struct addr_ctrl_blk *init_fw_cb;
  367. dma_addr_t init_fw_cb_dma;
  368. uint32_t mbox_cmd[MBOX_REG_COUNT];
  369. uint32_t mbox_sts[MBOX_REG_COUNT];
  370. int status = QLA_ERROR;
  371. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  372. sizeof(struct addr_ctrl_blk),
  373. &init_fw_cb_dma, GFP_KERNEL);
  374. if (init_fw_cb == NULL) {
  375. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  376. ha->host_no, __func__));
  377. goto exit_init_fw_cb_no_free;
  378. }
  379. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  380. /* Get Initialize Firmware Control Block. */
  381. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  382. memset(&mbox_sts, 0, sizeof(mbox_sts));
  383. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  384. QLA_SUCCESS) {
  385. dma_free_coherent(&ha->pdev->dev,
  386. sizeof(struct addr_ctrl_blk),
  387. init_fw_cb, init_fw_cb_dma);
  388. goto exit_init_fw_cb;
  389. }
  390. /* Initialize request and response queues. */
  391. qla4xxx_init_rings(ha);
  392. /* Fill in the request and response queue information. */
  393. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  394. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  395. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  396. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  397. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  398. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  399. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  400. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  401. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  402. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  403. /* Set up required options. */
  404. init_fw_cb->fw_options |=
  405. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  406. FWOPT_INITIATOR_MODE);
  407. if (is_qla8022(ha))
  408. init_fw_cb->fw_options |=
  409. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  410. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  411. /* Set bit for "serialize task mgmt" all other bits need to be zero */
  412. init_fw_cb->add_fw_options = 0;
  413. init_fw_cb->add_fw_options |=
  414. __constant_cpu_to_le16(SERIALIZE_TASK_MGMT);
  415. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  416. != QLA_SUCCESS) {
  417. DEBUG2(printk(KERN_WARNING
  418. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  419. ha->host_no, __func__));
  420. goto exit_init_fw_cb;
  421. }
  422. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  423. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  424. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  425. ha->host_no, __func__));
  426. goto exit_init_fw_cb;
  427. }
  428. status = QLA_SUCCESS;
  429. exit_init_fw_cb:
  430. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  431. init_fw_cb, init_fw_cb_dma);
  432. exit_init_fw_cb_no_free:
  433. return status;
  434. }
  435. /**
  436. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  437. * @ha: Pointer to host adapter structure.
  438. **/
  439. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  440. {
  441. struct addr_ctrl_blk *init_fw_cb;
  442. dma_addr_t init_fw_cb_dma;
  443. uint32_t mbox_cmd[MBOX_REG_COUNT];
  444. uint32_t mbox_sts[MBOX_REG_COUNT];
  445. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  446. sizeof(struct addr_ctrl_blk),
  447. &init_fw_cb_dma, GFP_KERNEL);
  448. if (init_fw_cb == NULL) {
  449. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  450. __func__);
  451. return QLA_ERROR;
  452. }
  453. /* Get Initialize Firmware Control Block. */
  454. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  455. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  456. QLA_SUCCESS) {
  457. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  458. ha->host_no, __func__));
  459. dma_free_coherent(&ha->pdev->dev,
  460. sizeof(struct addr_ctrl_blk),
  461. init_fw_cb, init_fw_cb_dma);
  462. return QLA_ERROR;
  463. }
  464. /* Save IP Address. */
  465. qla4xxx_update_local_ip(ha, init_fw_cb);
  466. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  467. init_fw_cb, init_fw_cb_dma);
  468. return QLA_SUCCESS;
  469. }
  470. /**
  471. * qla4xxx_get_firmware_state - gets firmware state of HBA
  472. * @ha: Pointer to host adapter structure.
  473. **/
  474. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  475. {
  476. uint32_t mbox_cmd[MBOX_REG_COUNT];
  477. uint32_t mbox_sts[MBOX_REG_COUNT];
  478. /* Get firmware version */
  479. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  480. memset(&mbox_sts, 0, sizeof(mbox_sts));
  481. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  482. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  483. QLA_SUCCESS) {
  484. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  485. "status %04X\n", ha->host_no, __func__,
  486. mbox_sts[0]));
  487. return QLA_ERROR;
  488. }
  489. ha->firmware_state = mbox_sts[1];
  490. ha->board_id = mbox_sts[2];
  491. ha->addl_fw_state = mbox_sts[3];
  492. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  493. ha->host_no, __func__, ha->firmware_state);)
  494. return QLA_SUCCESS;
  495. }
  496. /**
  497. * qla4xxx_get_firmware_status - retrieves firmware status
  498. * @ha: Pointer to host adapter structure.
  499. **/
  500. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  501. {
  502. uint32_t mbox_cmd[MBOX_REG_COUNT];
  503. uint32_t mbox_sts[MBOX_REG_COUNT];
  504. /* Get firmware version */
  505. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  506. memset(&mbox_sts, 0, sizeof(mbox_sts));
  507. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  508. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  509. QLA_SUCCESS) {
  510. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  511. "status %04X\n", ha->host_no, __func__,
  512. mbox_sts[0]));
  513. return QLA_ERROR;
  514. }
  515. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  516. ha->host_no, mbox_sts[2]);
  517. return QLA_SUCCESS;
  518. }
  519. /**
  520. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  521. * @ha: Pointer to host adapter structure.
  522. * @fw_ddb_index: Firmware's device database index
  523. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  524. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  525. * @next_ddb_index: Pointer to next valid device database index
  526. * @fw_ddb_device_state: Pointer to device state
  527. **/
  528. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  529. uint16_t fw_ddb_index,
  530. struct dev_db_entry *fw_ddb_entry,
  531. dma_addr_t fw_ddb_entry_dma,
  532. uint32_t *num_valid_ddb_entries,
  533. uint32_t *next_ddb_index,
  534. uint32_t *fw_ddb_device_state,
  535. uint32_t *conn_err_detail,
  536. uint16_t *tcp_source_port_num,
  537. uint16_t *connection_id)
  538. {
  539. int status = QLA_ERROR;
  540. uint16_t options;
  541. uint32_t mbox_cmd[MBOX_REG_COUNT];
  542. uint32_t mbox_sts[MBOX_REG_COUNT];
  543. /* Make sure the device index is valid */
  544. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  545. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  546. ha->host_no, __func__, fw_ddb_index));
  547. goto exit_get_fwddb;
  548. }
  549. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  550. memset(&mbox_sts, 0, sizeof(mbox_sts));
  551. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  552. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  553. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  554. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  555. mbox_cmd[4] = sizeof(struct dev_db_entry);
  556. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  557. QLA_ERROR) {
  558. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  559. " with status 0x%04X\n", ha->host_no, __func__,
  560. mbox_sts[0]));
  561. goto exit_get_fwddb;
  562. }
  563. if (fw_ddb_index != mbox_sts[1]) {
  564. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  565. ha->host_no, __func__, fw_ddb_index,
  566. mbox_sts[1]));
  567. goto exit_get_fwddb;
  568. }
  569. if (fw_ddb_entry) {
  570. options = le16_to_cpu(fw_ddb_entry->options);
  571. if (options & DDB_OPT_IPV6_DEVICE) {
  572. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  573. "Next %d State %04x ConnErr %08x %pI6 "
  574. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  575. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  576. mbox_sts[4], mbox_sts[5],
  577. fw_ddb_entry->ip_addr,
  578. le16_to_cpu(fw_ddb_entry->port),
  579. fw_ddb_entry->iscsi_name);
  580. } else {
  581. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  582. "Next %d State %04x ConnErr %08x %pI4 "
  583. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  584. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  585. mbox_sts[4], mbox_sts[5],
  586. fw_ddb_entry->ip_addr,
  587. le16_to_cpu(fw_ddb_entry->port),
  588. fw_ddb_entry->iscsi_name);
  589. }
  590. }
  591. if (num_valid_ddb_entries)
  592. *num_valid_ddb_entries = mbox_sts[2];
  593. if (next_ddb_index)
  594. *next_ddb_index = mbox_sts[3];
  595. if (fw_ddb_device_state)
  596. *fw_ddb_device_state = mbox_sts[4];
  597. /*
  598. * RA: This mailbox has been changed to pass connection error and
  599. * details. Its true for ISP4010 as per Version E - Not sure when it
  600. * was changed. Get the time2wait from the fw_dd_entry field :
  601. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  602. * struct.
  603. */
  604. if (conn_err_detail)
  605. *conn_err_detail = mbox_sts[5];
  606. if (tcp_source_port_num)
  607. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  608. if (connection_id)
  609. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  610. status = QLA_SUCCESS;
  611. exit_get_fwddb:
  612. return status;
  613. }
  614. /**
  615. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  616. * @ha: Pointer to host adapter structure.
  617. * @fw_ddb_index: Firmware's device database index
  618. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  619. *
  620. * This routine initializes or updates the adapter's device database
  621. * entry for the specified device. It also triggers a login for the
  622. * specified device. Therefore, it may also be used as a secondary
  623. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  624. **/
  625. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  626. dma_addr_t fw_ddb_entry_dma)
  627. {
  628. uint32_t mbox_cmd[MBOX_REG_COUNT];
  629. uint32_t mbox_sts[MBOX_REG_COUNT];
  630. int status;
  631. /* Do not wait for completion. The firmware will send us an
  632. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  633. */
  634. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  635. memset(&mbox_sts, 0, sizeof(mbox_sts));
  636. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  637. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  638. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  639. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  640. mbox_cmd[4] = sizeof(struct dev_db_entry);
  641. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  642. &mbox_sts[0]);
  643. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  644. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  645. return status;
  646. }
  647. /**
  648. * qla4xxx_get_crash_record - retrieves crash record.
  649. * @ha: Pointer to host adapter structure.
  650. *
  651. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  652. **/
  653. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  654. {
  655. uint32_t mbox_cmd[MBOX_REG_COUNT];
  656. uint32_t mbox_sts[MBOX_REG_COUNT];
  657. struct crash_record *crash_record = NULL;
  658. dma_addr_t crash_record_dma = 0;
  659. uint32_t crash_record_size = 0;
  660. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  661. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  662. /* Get size of crash record. */
  663. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  664. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  665. QLA_SUCCESS) {
  666. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  667. ha->host_no, __func__));
  668. goto exit_get_crash_record;
  669. }
  670. crash_record_size = mbox_sts[4];
  671. if (crash_record_size == 0) {
  672. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  673. ha->host_no, __func__));
  674. goto exit_get_crash_record;
  675. }
  676. /* Alloc Memory for Crash Record. */
  677. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  678. &crash_record_dma, GFP_KERNEL);
  679. if (crash_record == NULL)
  680. goto exit_get_crash_record;
  681. /* Get Crash Record. */
  682. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  683. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  684. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  685. mbox_cmd[2] = LSDW(crash_record_dma);
  686. mbox_cmd[3] = MSDW(crash_record_dma);
  687. mbox_cmd[4] = crash_record_size;
  688. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  689. QLA_SUCCESS)
  690. goto exit_get_crash_record;
  691. /* Dump Crash Record. */
  692. exit_get_crash_record:
  693. if (crash_record)
  694. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  695. crash_record, crash_record_dma);
  696. }
  697. /**
  698. * qla4xxx_get_conn_event_log - retrieves connection event log
  699. * @ha: Pointer to host adapter structure.
  700. **/
  701. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  702. {
  703. uint32_t mbox_cmd[MBOX_REG_COUNT];
  704. uint32_t mbox_sts[MBOX_REG_COUNT];
  705. struct conn_event_log_entry *event_log = NULL;
  706. dma_addr_t event_log_dma = 0;
  707. uint32_t event_log_size = 0;
  708. uint32_t num_valid_entries;
  709. uint32_t oldest_entry = 0;
  710. uint32_t max_event_log_entries;
  711. uint8_t i;
  712. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  713. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  714. /* Get size of crash record. */
  715. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  716. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  717. QLA_SUCCESS)
  718. goto exit_get_event_log;
  719. event_log_size = mbox_sts[4];
  720. if (event_log_size == 0)
  721. goto exit_get_event_log;
  722. /* Alloc Memory for Crash Record. */
  723. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  724. &event_log_dma, GFP_KERNEL);
  725. if (event_log == NULL)
  726. goto exit_get_event_log;
  727. /* Get Crash Record. */
  728. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  729. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  730. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  731. mbox_cmd[2] = LSDW(event_log_dma);
  732. mbox_cmd[3] = MSDW(event_log_dma);
  733. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  734. QLA_SUCCESS) {
  735. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  736. "log!\n", ha->host_no, __func__));
  737. goto exit_get_event_log;
  738. }
  739. /* Dump Event Log. */
  740. num_valid_entries = mbox_sts[1];
  741. max_event_log_entries = event_log_size /
  742. sizeof(struct conn_event_log_entry);
  743. if (num_valid_entries > max_event_log_entries)
  744. oldest_entry = num_valid_entries % max_event_log_entries;
  745. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  746. ha->host_no, num_valid_entries));
  747. if (ql4xextended_error_logging == 3) {
  748. if (oldest_entry == 0) {
  749. /* Circular Buffer has not wrapped around */
  750. for (i=0; i < num_valid_entries; i++) {
  751. qla4xxx_dump_buffer((uint8_t *)event_log+
  752. (i*sizeof(*event_log)),
  753. sizeof(*event_log));
  754. }
  755. }
  756. else {
  757. /* Circular Buffer has wrapped around -
  758. * display accordingly*/
  759. for (i=oldest_entry; i < max_event_log_entries; i++) {
  760. qla4xxx_dump_buffer((uint8_t *)event_log+
  761. (i*sizeof(*event_log)),
  762. sizeof(*event_log));
  763. }
  764. for (i=0; i < oldest_entry; i++) {
  765. qla4xxx_dump_buffer((uint8_t *)event_log+
  766. (i*sizeof(*event_log)),
  767. sizeof(*event_log));
  768. }
  769. }
  770. }
  771. exit_get_event_log:
  772. if (event_log)
  773. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  774. event_log_dma);
  775. }
  776. /**
  777. * qla4xxx_abort_task - issues Abort Task
  778. * @ha: Pointer to host adapter structure.
  779. * @srb: Pointer to srb entry
  780. *
  781. * This routine performs a LUN RESET on the specified target/lun.
  782. * The caller must ensure that the ddb_entry and lun_entry pointers
  783. * are valid before calling this routine.
  784. **/
  785. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  786. {
  787. uint32_t mbox_cmd[MBOX_REG_COUNT];
  788. uint32_t mbox_sts[MBOX_REG_COUNT];
  789. struct scsi_cmnd *cmd = srb->cmd;
  790. int status = QLA_SUCCESS;
  791. unsigned long flags = 0;
  792. uint32_t index;
  793. /*
  794. * Send abort task command to ISP, so that the ISP will return
  795. * request with ABORT status
  796. */
  797. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  798. memset(&mbox_sts, 0, sizeof(mbox_sts));
  799. spin_lock_irqsave(&ha->hardware_lock, flags);
  800. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  801. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  802. /* Firmware already posted completion on response queue */
  803. if (index == MAX_SRBS)
  804. return status;
  805. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  806. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  807. mbox_cmd[2] = index;
  808. /* Immediate Command Enable */
  809. mbox_cmd[5] = 0x01;
  810. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  811. &mbox_sts[0]);
  812. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  813. status = QLA_ERROR;
  814. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  815. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  816. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  817. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  818. }
  819. return status;
  820. }
  821. /**
  822. * qla4xxx_reset_lun - issues LUN Reset
  823. * @ha: Pointer to host adapter structure.
  824. * @ddb_entry: Pointer to device database entry
  825. * @lun: lun number
  826. *
  827. * This routine performs a LUN RESET on the specified target/lun.
  828. * The caller must ensure that the ddb_entry and lun_entry pointers
  829. * are valid before calling this routine.
  830. **/
  831. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  832. int lun)
  833. {
  834. uint32_t mbox_cmd[MBOX_REG_COUNT];
  835. uint32_t mbox_sts[MBOX_REG_COUNT];
  836. int status = QLA_SUCCESS;
  837. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  838. ddb_entry->fw_ddb_index, lun));
  839. /*
  840. * Send lun reset command to ISP, so that the ISP will return all
  841. * outstanding requests with RESET status
  842. */
  843. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  844. memset(&mbox_sts, 0, sizeof(mbox_sts));
  845. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  846. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  847. mbox_cmd[2] = lun << 8;
  848. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  849. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  850. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  851. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  852. status = QLA_ERROR;
  853. return status;
  854. }
  855. /**
  856. * qla4xxx_reset_target - issues target Reset
  857. * @ha: Pointer to host adapter structure.
  858. * @db_entry: Pointer to device database entry
  859. * @un_entry: Pointer to lun entry structure
  860. *
  861. * This routine performs a TARGET RESET on the specified target.
  862. * The caller must ensure that the ddb_entry pointers
  863. * are valid before calling this routine.
  864. **/
  865. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  866. struct ddb_entry *ddb_entry)
  867. {
  868. uint32_t mbox_cmd[MBOX_REG_COUNT];
  869. uint32_t mbox_sts[MBOX_REG_COUNT];
  870. int status = QLA_SUCCESS;
  871. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  872. ddb_entry->fw_ddb_index));
  873. /*
  874. * Send target reset command to ISP, so that the ISP will return all
  875. * outstanding requests with RESET status
  876. */
  877. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  878. memset(&mbox_sts, 0, sizeof(mbox_sts));
  879. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  880. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  881. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  882. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  883. &mbox_sts[0]);
  884. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  885. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  886. status = QLA_ERROR;
  887. return status;
  888. }
  889. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  890. uint32_t offset, uint32_t len)
  891. {
  892. uint32_t mbox_cmd[MBOX_REG_COUNT];
  893. uint32_t mbox_sts[MBOX_REG_COUNT];
  894. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  895. memset(&mbox_sts, 0, sizeof(mbox_sts));
  896. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  897. mbox_cmd[1] = LSDW(dma_addr);
  898. mbox_cmd[2] = MSDW(dma_addr);
  899. mbox_cmd[3] = offset;
  900. mbox_cmd[4] = len;
  901. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  902. QLA_SUCCESS) {
  903. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  904. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  905. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  906. return QLA_ERROR;
  907. }
  908. return QLA_SUCCESS;
  909. }
  910. /**
  911. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  912. * @ha: Pointer to host adapter structure.
  913. *
  914. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  915. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  916. * those mailboxes, if unused.
  917. **/
  918. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  919. {
  920. struct about_fw_info *about_fw = NULL;
  921. dma_addr_t about_fw_dma;
  922. uint32_t mbox_cmd[MBOX_REG_COUNT];
  923. uint32_t mbox_sts[MBOX_REG_COUNT];
  924. int status = QLA_ERROR;
  925. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  926. sizeof(struct about_fw_info),
  927. &about_fw_dma, GFP_KERNEL);
  928. if (!about_fw) {
  929. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  930. "for about_fw\n", __func__));
  931. return status;
  932. }
  933. memset(about_fw, 0, sizeof(struct about_fw_info));
  934. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  935. memset(&mbox_sts, 0, sizeof(mbox_sts));
  936. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  937. mbox_cmd[2] = LSDW(about_fw_dma);
  938. mbox_cmd[3] = MSDW(about_fw_dma);
  939. mbox_cmd[4] = sizeof(struct about_fw_info);
  940. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  941. &mbox_cmd[0], &mbox_sts[0]);
  942. if (status != QLA_SUCCESS) {
  943. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  944. "failed w/ status %04X\n", __func__,
  945. mbox_sts[0]));
  946. goto exit_about_fw;
  947. }
  948. /* Save version information. */
  949. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  950. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  951. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  952. ha->build_number = le16_to_cpu(about_fw->fw_build);
  953. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  954. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  955. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  956. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  957. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  958. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  959. status = QLA_SUCCESS;
  960. exit_about_fw:
  961. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  962. about_fw, about_fw_dma);
  963. return status;
  964. }
  965. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  966. dma_addr_t dma_addr)
  967. {
  968. uint32_t mbox_cmd[MBOX_REG_COUNT];
  969. uint32_t mbox_sts[MBOX_REG_COUNT];
  970. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  971. memset(&mbox_sts, 0, sizeof(mbox_sts));
  972. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  973. mbox_cmd[2] = LSDW(dma_addr);
  974. mbox_cmd[3] = MSDW(dma_addr);
  975. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  976. QLA_SUCCESS) {
  977. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  978. ha->host_no, __func__, mbox_sts[0]));
  979. return QLA_ERROR;
  980. }
  981. return QLA_SUCCESS;
  982. }
  983. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  984. {
  985. uint32_t mbox_cmd[MBOX_REG_COUNT];
  986. uint32_t mbox_sts[MBOX_REG_COUNT];
  987. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  988. memset(&mbox_sts, 0, sizeof(mbox_sts));
  989. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  990. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  991. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  992. QLA_SUCCESS) {
  993. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  994. *ddb_index = mbox_sts[2];
  995. } else {
  996. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  997. ha->host_no, __func__, mbox_sts[0]));
  998. return QLA_ERROR;
  999. }
  1000. } else {
  1001. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  1002. }
  1003. return QLA_SUCCESS;
  1004. }
  1005. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  1006. {
  1007. struct dev_db_entry *fw_ddb_entry;
  1008. dma_addr_t fw_ddb_entry_dma;
  1009. uint32_t ddb_index;
  1010. int ret_val = QLA_SUCCESS;
  1011. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  1012. sizeof(*fw_ddb_entry),
  1013. &fw_ddb_entry_dma, GFP_KERNEL);
  1014. if (!fw_ddb_entry) {
  1015. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  1016. ha->host_no, __func__));
  1017. ret_val = QLA_ERROR;
  1018. goto exit_send_tgts_no_free;
  1019. }
  1020. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  1021. if (ret_val != QLA_SUCCESS)
  1022. goto exit_send_tgts;
  1023. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  1024. if (ret_val != QLA_SUCCESS)
  1025. goto exit_send_tgts;
  1026. memset(fw_ddb_entry->iscsi_alias, 0,
  1027. sizeof(fw_ddb_entry->iscsi_alias));
  1028. memset(fw_ddb_entry->iscsi_name, 0,
  1029. sizeof(fw_ddb_entry->iscsi_name));
  1030. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1031. memset(fw_ddb_entry->tgt_addr, 0,
  1032. sizeof(fw_ddb_entry->tgt_addr));
  1033. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  1034. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  1035. fw_ddb_entry->ip_addr[0] = *ip;
  1036. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  1037. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  1038. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  1039. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  1040. exit_send_tgts:
  1041. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1042. fw_ddb_entry, fw_ddb_entry_dma);
  1043. exit_send_tgts_no_free:
  1044. return ret_val;
  1045. }