bnx2fc_hwi.c 53 KB

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  1. /* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2010 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation.
  10. *
  11. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  12. */
  13. #include "bnx2fc.h"
  14. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  15. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  16. struct fcoe_kcqe *new_cqe_kcqe);
  17. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *ofld_kcqe);
  19. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  22. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  23. struct fcoe_kcqe *conn_destroy);
  24. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  25. {
  26. struct fcoe_kwqe_stat stat_req;
  27. struct kwqe *kwqe_arr[2];
  28. int num_kwqes = 1;
  29. int rc = 0;
  30. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  31. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  32. stat_req.hdr.flags =
  33. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  34. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  35. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  36. kwqe_arr[0] = (struct kwqe *) &stat_req;
  37. if (hba->cnic && hba->cnic->submit_kwqes)
  38. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  39. return rc;
  40. }
  41. /**
  42. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  43. *
  44. * @hba: adapter structure pointer
  45. *
  46. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  47. * with the f/w.
  48. *
  49. */
  50. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  51. {
  52. struct fcoe_kwqe_init1 fcoe_init1;
  53. struct fcoe_kwqe_init2 fcoe_init2;
  54. struct fcoe_kwqe_init3 fcoe_init3;
  55. struct kwqe *kwqe_arr[3];
  56. int num_kwqes = 3;
  57. int rc = 0;
  58. if (!hba->cnic) {
  59. printk(KERN_ALERT PFX "hba->cnic NULL during fcoe fw init\n");
  60. return -ENODEV;
  61. }
  62. /* fill init1 KWQE */
  63. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  64. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  65. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  66. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  67. fcoe_init1.num_tasks = BNX2FC_MAX_TASKS;
  68. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  69. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  70. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  71. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  72. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  73. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  74. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  75. fcoe_init1.task_list_pbl_addr_hi =
  76. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  77. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  78. fcoe_init1.flags = (PAGE_SHIFT <<
  79. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  80. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  81. /* fill init2 KWQE */
  82. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  83. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  84. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  85. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  86. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  87. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  88. ((u64) hba->hash_tbl_pbl_dma >> 32);
  89. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  90. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  91. ((u64) hba->t2_hash_tbl_dma >> 32);
  92. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  93. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  94. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  95. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  96. /* fill init3 KWQE */
  97. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  98. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  99. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  100. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  101. fcoe_init3.error_bit_map_lo = 0xffffffff;
  102. fcoe_init3.error_bit_map_hi = 0xffffffff;
  103. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  104. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  105. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  106. if (hba->cnic && hba->cnic->submit_kwqes)
  107. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  108. return rc;
  109. }
  110. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  111. {
  112. struct fcoe_kwqe_destroy fcoe_destroy;
  113. struct kwqe *kwqe_arr[2];
  114. int num_kwqes = 1;
  115. int rc = -1;
  116. /* fill destroy KWQE */
  117. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  118. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  119. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  120. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  121. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  122. if (hba->cnic && hba->cnic->submit_kwqes)
  123. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  124. return rc;
  125. }
  126. /**
  127. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  128. *
  129. * @port: port structure pointer
  130. * @tgt: bnx2fc_rport structure pointer
  131. */
  132. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  133. struct bnx2fc_rport *tgt)
  134. {
  135. struct fc_lport *lport = port->lport;
  136. struct bnx2fc_hba *hba = port->priv;
  137. struct kwqe *kwqe_arr[4];
  138. struct fcoe_kwqe_conn_offload1 ofld_req1;
  139. struct fcoe_kwqe_conn_offload2 ofld_req2;
  140. struct fcoe_kwqe_conn_offload3 ofld_req3;
  141. struct fcoe_kwqe_conn_offload4 ofld_req4;
  142. struct fc_rport_priv *rdata = tgt->rdata;
  143. struct fc_rport *rport = tgt->rport;
  144. int num_kwqes = 4;
  145. u32 port_id;
  146. int rc = 0;
  147. u16 conn_id;
  148. /* Initialize offload request 1 structure */
  149. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  150. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  151. ofld_req1.hdr.flags =
  152. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  153. conn_id = (u16)tgt->fcoe_conn_id;
  154. ofld_req1.fcoe_conn_id = conn_id;
  155. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  156. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  157. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  158. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  159. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  160. ofld_req1.rq_first_pbe_addr_hi =
  161. (u32)((u64) tgt->rq_dma >> 32);
  162. ofld_req1.rq_prod = 0x8000;
  163. /* Initialize offload request 2 structure */
  164. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  165. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  166. ofld_req2.hdr.flags =
  167. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  168. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  169. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  170. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  171. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  172. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  173. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  174. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  175. /* Initialize offload request 3 structure */
  176. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  177. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  178. ofld_req3.hdr.flags =
  179. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  180. ofld_req3.vlan_tag = hba->vlan_id <<
  181. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  182. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  183. port_id = fc_host_port_id(lport->host);
  184. if (port_id == 0) {
  185. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  186. return -EINVAL;
  187. }
  188. /*
  189. * Store s_id of the initiator for further reference. This will
  190. * be used during disable/destroy during linkdown processing as
  191. * when the lport is reset, the port_id also is reset to 0
  192. */
  193. tgt->sid = port_id;
  194. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  195. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  196. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  197. port_id = rport->port_id;
  198. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  199. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  200. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  201. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  202. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  203. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  204. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  205. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  206. ofld_req3.rx_open_seqs_exch_c3 = 1;
  207. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  208. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  209. /* set mul_n_port_ids supported flag to 0, until it is supported */
  210. ofld_req3.flags = 0;
  211. /*
  212. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  213. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  214. */
  215. /* Info from PLOGI response */
  216. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  217. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  218. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  219. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  220. /* vlan flag */
  221. ofld_req3.flags |= (hba->vlan_enabled <<
  222. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  223. /* C2_VALID and ACK flags are not set as they are not suppported */
  224. /* Initialize offload request 4 structure */
  225. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  226. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  227. ofld_req4.hdr.flags =
  228. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  229. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  230. ofld_req4.src_mac_addr_lo32[0] = port->data_src_addr[5];
  231. /* local mac */
  232. ofld_req4.src_mac_addr_lo32[1] = port->data_src_addr[4];
  233. ofld_req4.src_mac_addr_lo32[2] = port->data_src_addr[3];
  234. ofld_req4.src_mac_addr_lo32[3] = port->data_src_addr[2];
  235. ofld_req4.src_mac_addr_hi16[0] = port->data_src_addr[1];
  236. ofld_req4.src_mac_addr_hi16[1] = port->data_src_addr[0];
  237. ofld_req4.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  238. ofld_req4.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  239. ofld_req4.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  240. ofld_req4.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  241. ofld_req4.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  242. ofld_req4.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  243. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  244. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  245. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  246. ofld_req4.confq_pbl_base_addr_hi =
  247. (u32)((u64) tgt->confq_pbl_dma >> 32);
  248. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  249. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  250. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  251. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  252. if (hba->cnic && hba->cnic->submit_kwqes)
  253. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  254. return rc;
  255. }
  256. /**
  257. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  258. *
  259. * @port: port structure pointer
  260. * @tgt: bnx2fc_rport structure pointer
  261. */
  262. static int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  263. struct bnx2fc_rport *tgt)
  264. {
  265. struct kwqe *kwqe_arr[2];
  266. struct bnx2fc_hba *hba = port->priv;
  267. struct fcoe_kwqe_conn_enable_disable enbl_req;
  268. struct fc_lport *lport = port->lport;
  269. struct fc_rport *rport = tgt->rport;
  270. int num_kwqes = 1;
  271. int rc = 0;
  272. u32 port_id;
  273. memset(&enbl_req, 0x00,
  274. sizeof(struct fcoe_kwqe_conn_enable_disable));
  275. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  276. enbl_req.hdr.flags =
  277. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  278. enbl_req.src_mac_addr_lo32[0] = port->data_src_addr[5];
  279. /* local mac */
  280. enbl_req.src_mac_addr_lo32[1] = port->data_src_addr[4];
  281. enbl_req.src_mac_addr_lo32[2] = port->data_src_addr[3];
  282. enbl_req.src_mac_addr_lo32[3] = port->data_src_addr[2];
  283. enbl_req.src_mac_addr_hi16[0] = port->data_src_addr[1];
  284. enbl_req.src_mac_addr_hi16[1] = port->data_src_addr[0];
  285. enbl_req.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  286. enbl_req.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  287. enbl_req.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  288. enbl_req.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  289. enbl_req.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  290. enbl_req.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  291. port_id = fc_host_port_id(lport->host);
  292. if (port_id != tgt->sid) {
  293. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  294. "sid = 0x%x\n", port_id, tgt->sid);
  295. port_id = tgt->sid;
  296. }
  297. enbl_req.s_id[0] = (port_id & 0x000000FF);
  298. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  299. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  300. port_id = rport->port_id;
  301. enbl_req.d_id[0] = (port_id & 0x000000FF);
  302. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  303. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  304. enbl_req.vlan_tag = hba->vlan_id <<
  305. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  306. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  307. enbl_req.vlan_flag = hba->vlan_enabled;
  308. enbl_req.context_id = tgt->context_id;
  309. enbl_req.conn_id = tgt->fcoe_conn_id;
  310. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  311. if (hba->cnic && hba->cnic->submit_kwqes)
  312. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  313. return rc;
  314. }
  315. /**
  316. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  317. *
  318. * @port: port structure pointer
  319. * @tgt: bnx2fc_rport structure pointer
  320. */
  321. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  322. struct bnx2fc_rport *tgt)
  323. {
  324. struct bnx2fc_hba *hba = port->priv;
  325. struct fcoe_kwqe_conn_enable_disable disable_req;
  326. struct kwqe *kwqe_arr[2];
  327. struct fc_rport *rport = tgt->rport;
  328. int num_kwqes = 1;
  329. int rc = 0;
  330. u32 port_id;
  331. memset(&disable_req, 0x00,
  332. sizeof(struct fcoe_kwqe_conn_enable_disable));
  333. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  334. disable_req.hdr.flags =
  335. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  336. disable_req.src_mac_addr_lo32[0] = port->data_src_addr[5];
  337. disable_req.src_mac_addr_lo32[2] = port->data_src_addr[3];
  338. disable_req.src_mac_addr_lo32[3] = port->data_src_addr[2];
  339. disable_req.src_mac_addr_hi16[0] = port->data_src_addr[1];
  340. disable_req.src_mac_addr_hi16[1] = port->data_src_addr[0];
  341. disable_req.dst_mac_addr_lo32[0] = hba->ctlr.dest_addr[5];/* fcf mac */
  342. disable_req.dst_mac_addr_lo32[1] = hba->ctlr.dest_addr[4];
  343. disable_req.dst_mac_addr_lo32[2] = hba->ctlr.dest_addr[3];
  344. disable_req.dst_mac_addr_lo32[3] = hba->ctlr.dest_addr[2];
  345. disable_req.dst_mac_addr_hi16[0] = hba->ctlr.dest_addr[1];
  346. disable_req.dst_mac_addr_hi16[1] = hba->ctlr.dest_addr[0];
  347. port_id = tgt->sid;
  348. disable_req.s_id[0] = (port_id & 0x000000FF);
  349. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  350. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  351. port_id = rport->port_id;
  352. disable_req.d_id[0] = (port_id & 0x000000FF);
  353. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  354. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  355. disable_req.context_id = tgt->context_id;
  356. disable_req.conn_id = tgt->fcoe_conn_id;
  357. disable_req.vlan_tag = hba->vlan_id <<
  358. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  359. disable_req.vlan_tag |=
  360. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  361. disable_req.vlan_flag = hba->vlan_enabled;
  362. kwqe_arr[0] = (struct kwqe *) &disable_req;
  363. if (hba->cnic && hba->cnic->submit_kwqes)
  364. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  365. return rc;
  366. }
  367. /**
  368. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  369. *
  370. * @port: port structure pointer
  371. * @tgt: bnx2fc_rport structure pointer
  372. */
  373. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  374. struct bnx2fc_rport *tgt)
  375. {
  376. struct fcoe_kwqe_conn_destroy destroy_req;
  377. struct kwqe *kwqe_arr[2];
  378. int num_kwqes = 1;
  379. int rc = 0;
  380. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  381. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  382. destroy_req.hdr.flags =
  383. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  384. destroy_req.context_id = tgt->context_id;
  385. destroy_req.conn_id = tgt->fcoe_conn_id;
  386. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  387. if (hba->cnic && hba->cnic->submit_kwqes)
  388. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  389. return rc;
  390. }
  391. static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
  392. {
  393. struct bnx2fc_lport *blport;
  394. spin_lock_bh(&hba->hba_lock);
  395. list_for_each_entry(blport, &hba->vports, list) {
  396. if (blport->lport == lport) {
  397. spin_unlock_bh(&hba->hba_lock);
  398. return true;
  399. }
  400. }
  401. spin_unlock_bh(&hba->hba_lock);
  402. return false;
  403. }
  404. static void bnx2fc_unsol_els_work(struct work_struct *work)
  405. {
  406. struct bnx2fc_unsol_els *unsol_els;
  407. struct fc_lport *lport;
  408. struct bnx2fc_hba *hba;
  409. struct fc_frame *fp;
  410. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  411. lport = unsol_els->lport;
  412. fp = unsol_els->fp;
  413. hba = unsol_els->hba;
  414. if (is_valid_lport(hba, lport))
  415. fc_exch_recv(lport, fp);
  416. kfree(unsol_els);
  417. }
  418. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  419. unsigned char *buf,
  420. u32 frame_len, u16 l2_oxid)
  421. {
  422. struct fcoe_port *port = tgt->port;
  423. struct fc_lport *lport = port->lport;
  424. struct bnx2fc_hba *hba = port->priv;
  425. struct bnx2fc_unsol_els *unsol_els;
  426. struct fc_frame_header *fh;
  427. struct fc_frame *fp;
  428. struct sk_buff *skb;
  429. u32 payload_len;
  430. u32 crc;
  431. u8 op;
  432. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  433. if (!unsol_els) {
  434. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  435. return;
  436. }
  437. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  438. l2_oxid, frame_len);
  439. payload_len = frame_len - sizeof(struct fc_frame_header);
  440. fp = fc_frame_alloc(lport, payload_len);
  441. if (!fp) {
  442. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  443. kfree(unsol_els);
  444. return;
  445. }
  446. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  447. /* Copy FC Frame header and payload into the frame */
  448. memcpy(fh, buf, frame_len);
  449. if (l2_oxid != FC_XID_UNKNOWN)
  450. fh->fh_ox_id = htons(l2_oxid);
  451. skb = fp_skb(fp);
  452. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  453. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  454. if (fh->fh_type == FC_TYPE_ELS) {
  455. op = fc_frame_payload_op(fp);
  456. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  457. (op == ELS_FAN) || (op == ELS_CSU)) {
  458. /*
  459. * No need to reply for these
  460. * ELS requests
  461. */
  462. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  463. kfree_skb(skb);
  464. kfree(unsol_els);
  465. return;
  466. }
  467. }
  468. crc = fcoe_fc_crc(fp);
  469. fc_frame_init(fp);
  470. fr_dev(fp) = lport;
  471. fr_sof(fp) = FC_SOF_I3;
  472. fr_eof(fp) = FC_EOF_T;
  473. fr_crc(fp) = cpu_to_le32(~crc);
  474. unsol_els->lport = lport;
  475. unsol_els->hba = hba;
  476. unsol_els->fp = fp;
  477. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  478. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  479. } else {
  480. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  481. kfree_skb(skb);
  482. kfree(unsol_els);
  483. }
  484. }
  485. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  486. {
  487. u8 num_rq;
  488. struct fcoe_err_report_entry *err_entry;
  489. unsigned char *rq_data;
  490. unsigned char *buf = NULL, *buf1;
  491. int i;
  492. u16 xid;
  493. u32 frame_len, len;
  494. struct bnx2fc_cmd *io_req = NULL;
  495. struct fcoe_task_ctx_entry *task, *task_page;
  496. struct bnx2fc_hba *hba = tgt->port->priv;
  497. int task_idx, index;
  498. int rc = 0;
  499. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  500. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  501. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  502. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  503. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  504. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  505. spin_lock_bh(&tgt->tgt_lock);
  506. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  507. spin_unlock_bh(&tgt->tgt_lock);
  508. if (rq_data) {
  509. buf = rq_data;
  510. } else {
  511. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  512. GFP_ATOMIC);
  513. if (!buf1) {
  514. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  515. break;
  516. }
  517. for (i = 0; i < num_rq; i++) {
  518. spin_lock_bh(&tgt->tgt_lock);
  519. rq_data = (unsigned char *)
  520. bnx2fc_get_next_rqe(tgt, 1);
  521. spin_unlock_bh(&tgt->tgt_lock);
  522. len = BNX2FC_RQ_BUF_SZ;
  523. memcpy(buf1, rq_data, len);
  524. buf1 += len;
  525. }
  526. }
  527. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  528. FC_XID_UNKNOWN);
  529. if (buf != rq_data)
  530. kfree(buf);
  531. spin_lock_bh(&tgt->tgt_lock);
  532. bnx2fc_return_rqe(tgt, num_rq);
  533. spin_unlock_bh(&tgt->tgt_lock);
  534. break;
  535. case FCOE_ERROR_DETECTION_CQE_TYPE:
  536. /*
  537. * In case of error reporting CQE a single RQ entry
  538. * is consumed.
  539. */
  540. spin_lock_bh(&tgt->tgt_lock);
  541. num_rq = 1;
  542. err_entry = (struct fcoe_err_report_entry *)
  543. bnx2fc_get_next_rqe(tgt, 1);
  544. xid = err_entry->fc_hdr.ox_id;
  545. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  546. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  547. err_entry->err_warn_bitmap_hi,
  548. err_entry->err_warn_bitmap_lo);
  549. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  550. err_entry->tx_buf_off, err_entry->rx_buf_off);
  551. bnx2fc_return_rqe(tgt, 1);
  552. if (xid > BNX2FC_MAX_XID) {
  553. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  554. xid);
  555. spin_unlock_bh(&tgt->tgt_lock);
  556. break;
  557. }
  558. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  559. index = xid % BNX2FC_TASKS_PER_PAGE;
  560. task_page = (struct fcoe_task_ctx_entry *)
  561. hba->task_ctx[task_idx];
  562. task = &(task_page[index]);
  563. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  564. if (!io_req) {
  565. spin_unlock_bh(&tgt->tgt_lock);
  566. break;
  567. }
  568. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  569. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  570. spin_unlock_bh(&tgt->tgt_lock);
  571. break;
  572. }
  573. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  574. &io_req->req_flags)) {
  575. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  576. "progress.. ignore unsol err\n");
  577. spin_unlock_bh(&tgt->tgt_lock);
  578. break;
  579. }
  580. /*
  581. * If ABTS is already in progress, and FW error is
  582. * received after that, do not cancel the timeout_work
  583. * and let the error recovery continue by explicitly
  584. * logging out the target, when the ABTS eventually
  585. * times out.
  586. */
  587. if (!test_and_set_bit(BNX2FC_FLAG_ISSUE_ABTS,
  588. &io_req->req_flags)) {
  589. /*
  590. * Cancel the timeout_work, as we received IO
  591. * completion with FW error.
  592. */
  593. if (cancel_delayed_work(&io_req->timeout_work))
  594. kref_put(&io_req->refcount,
  595. bnx2fc_cmd_release); /* timer hold */
  596. rc = bnx2fc_initiate_abts(io_req);
  597. if (rc != SUCCESS) {
  598. BNX2FC_IO_DBG(io_req, "err_warn: initiate_abts "
  599. "failed. issue cleanup\n");
  600. rc = bnx2fc_initiate_cleanup(io_req);
  601. BUG_ON(rc);
  602. }
  603. } else
  604. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  605. "in ABTS processing\n", xid);
  606. spin_unlock_bh(&tgt->tgt_lock);
  607. break;
  608. case FCOE_WARNING_DETECTION_CQE_TYPE:
  609. /*
  610. *In case of warning reporting CQE a single RQ entry
  611. * is consumes.
  612. */
  613. spin_lock_bh(&tgt->tgt_lock);
  614. num_rq = 1;
  615. err_entry = (struct fcoe_err_report_entry *)
  616. bnx2fc_get_next_rqe(tgt, 1);
  617. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  618. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  619. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  620. err_entry->err_warn_bitmap_hi,
  621. err_entry->err_warn_bitmap_lo);
  622. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  623. err_entry->tx_buf_off, err_entry->rx_buf_off);
  624. bnx2fc_return_rqe(tgt, 1);
  625. spin_unlock_bh(&tgt->tgt_lock);
  626. break;
  627. default:
  628. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  629. break;
  630. }
  631. }
  632. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  633. {
  634. struct fcoe_task_ctx_entry *task;
  635. struct fcoe_task_ctx_entry *task_page;
  636. struct fcoe_port *port = tgt->port;
  637. struct bnx2fc_hba *hba = port->priv;
  638. struct bnx2fc_cmd *io_req;
  639. int task_idx, index;
  640. u16 xid;
  641. u8 cmd_type;
  642. u8 rx_state = 0;
  643. u8 num_rq;
  644. spin_lock_bh(&tgt->tgt_lock);
  645. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  646. if (xid >= BNX2FC_MAX_TASKS) {
  647. printk(KERN_ALERT PFX "ERROR:xid out of range\n");
  648. spin_unlock_bh(&tgt->tgt_lock);
  649. return;
  650. }
  651. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  652. index = xid % BNX2FC_TASKS_PER_PAGE;
  653. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  654. task = &(task_page[index]);
  655. num_rq = ((task->rx_wr_tx_rd.rx_flags &
  656. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE) >>
  657. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT);
  658. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  659. if (io_req == NULL) {
  660. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  661. spin_unlock_bh(&tgt->tgt_lock);
  662. return;
  663. }
  664. /* Timestamp IO completion time */
  665. cmd_type = io_req->cmd_type;
  666. /* optimized completion path */
  667. if (cmd_type == BNX2FC_SCSI_CMD) {
  668. rx_state = ((task->rx_wr_tx_rd.rx_flags &
  669. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE) >>
  670. FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT);
  671. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  672. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  673. spin_unlock_bh(&tgt->tgt_lock);
  674. return;
  675. }
  676. }
  677. /* Process other IO completion types */
  678. switch (cmd_type) {
  679. case BNX2FC_SCSI_CMD:
  680. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  681. bnx2fc_process_abts_compl(io_req, task, num_rq);
  682. else if (rx_state ==
  683. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  684. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  685. else
  686. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  687. rx_state);
  688. break;
  689. case BNX2FC_TASK_MGMT_CMD:
  690. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  691. bnx2fc_process_tm_compl(io_req, task, num_rq);
  692. break;
  693. case BNX2FC_ABTS:
  694. /*
  695. * ABTS request received by firmware. ABTS response
  696. * will be delivered to the task belonging to the IO
  697. * that was aborted
  698. */
  699. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  700. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  701. break;
  702. case BNX2FC_ELS:
  703. BNX2FC_IO_DBG(io_req, "cq_compl - call process_els_compl\n");
  704. bnx2fc_process_els_compl(io_req, task, num_rq);
  705. break;
  706. case BNX2FC_CLEANUP:
  707. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  708. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  709. break;
  710. default:
  711. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  712. break;
  713. }
  714. spin_unlock_bh(&tgt->tgt_lock);
  715. }
  716. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  717. {
  718. struct bnx2fc_work *work;
  719. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  720. if (!work)
  721. return NULL;
  722. INIT_LIST_HEAD(&work->list);
  723. work->tgt = tgt;
  724. work->wqe = wqe;
  725. return work;
  726. }
  727. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  728. {
  729. struct fcoe_cqe *cq;
  730. u32 cq_cons;
  731. struct fcoe_cqe *cqe;
  732. u16 wqe;
  733. bool more_cqes_found = false;
  734. /*
  735. * cq_lock is a low contention lock used to protect
  736. * the CQ data structure from being freed up during
  737. * the upload operation
  738. */
  739. spin_lock_bh(&tgt->cq_lock);
  740. if (!tgt->cq) {
  741. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  742. spin_unlock_bh(&tgt->cq_lock);
  743. return 0;
  744. }
  745. cq = tgt->cq;
  746. cq_cons = tgt->cq_cons_idx;
  747. cqe = &cq[cq_cons];
  748. do {
  749. more_cqes_found ^= true;
  750. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  751. (tgt->cq_curr_toggle_bit <<
  752. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  753. /* new entry on the cq */
  754. if (wqe & FCOE_CQE_CQE_TYPE) {
  755. /* Unsolicited event notification */
  756. bnx2fc_process_unsol_compl(tgt, wqe);
  757. } else {
  758. struct bnx2fc_work *work = NULL;
  759. struct bnx2fc_percpu_s *fps = NULL;
  760. unsigned int cpu = wqe % num_possible_cpus();
  761. fps = &per_cpu(bnx2fc_percpu, cpu);
  762. spin_lock_bh(&fps->fp_work_lock);
  763. if (unlikely(!fps->iothread))
  764. goto unlock;
  765. work = bnx2fc_alloc_work(tgt, wqe);
  766. if (work)
  767. list_add_tail(&work->list,
  768. &fps->work_list);
  769. unlock:
  770. spin_unlock_bh(&fps->fp_work_lock);
  771. /* Pending work request completion */
  772. if (fps->iothread && work)
  773. wake_up_process(fps->iothread);
  774. else
  775. bnx2fc_process_cq_compl(tgt, wqe);
  776. }
  777. cqe++;
  778. tgt->cq_cons_idx++;
  779. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  780. tgt->cq_cons_idx = 0;
  781. cqe = cq;
  782. tgt->cq_curr_toggle_bit =
  783. 1 - tgt->cq_curr_toggle_bit;
  784. }
  785. }
  786. /* Re-arm CQ */
  787. if (more_cqes_found) {
  788. tgt->conn_db->cq_arm.lo = -1;
  789. wmb();
  790. }
  791. } while (more_cqes_found);
  792. /*
  793. * Commit tgt->cq_cons_idx change to the memory
  794. * spin_lock implies full memory barrier, no need to smp_wmb
  795. */
  796. spin_unlock_bh(&tgt->cq_lock);
  797. return 0;
  798. }
  799. /**
  800. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  801. *
  802. * @hba: adapter structure pointer
  803. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  804. *
  805. * Fast path event notification handler
  806. */
  807. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  808. struct fcoe_kcqe *new_cqe_kcqe)
  809. {
  810. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  811. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  812. if (!tgt) {
  813. printk(KERN_ALERT PFX "conn_id 0x%x not valid\n", conn_id);
  814. return;
  815. }
  816. bnx2fc_process_new_cqes(tgt);
  817. }
  818. /**
  819. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  820. *
  821. * @hba: adapter structure pointer
  822. * @ofld_kcqe: connection offload kcqe pointer
  823. *
  824. * handle session offload completion, enable the session if offload is
  825. * successful.
  826. */
  827. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  828. struct fcoe_kcqe *ofld_kcqe)
  829. {
  830. struct bnx2fc_rport *tgt;
  831. struct fcoe_port *port;
  832. u32 conn_id;
  833. u32 context_id;
  834. int rc;
  835. conn_id = ofld_kcqe->fcoe_conn_id;
  836. context_id = ofld_kcqe->fcoe_conn_context_id;
  837. tgt = hba->tgt_ofld_list[conn_id];
  838. if (!tgt) {
  839. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  840. return;
  841. }
  842. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  843. ofld_kcqe->fcoe_conn_context_id);
  844. port = tgt->port;
  845. if (hba != tgt->port->priv) {
  846. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  847. goto ofld_cmpl_err;
  848. }
  849. /*
  850. * cnic has allocated a context_id for this session; use this
  851. * while enabling the session.
  852. */
  853. tgt->context_id = context_id;
  854. if (ofld_kcqe->completion_status) {
  855. if (ofld_kcqe->completion_status ==
  856. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  857. printk(KERN_ERR PFX "unable to allocate FCoE context "
  858. "resources\n");
  859. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  860. }
  861. goto ofld_cmpl_err;
  862. } else {
  863. /* now enable the session */
  864. rc = bnx2fc_send_session_enable_req(port, tgt);
  865. if (rc) {
  866. printk(KERN_ALERT PFX "enable session failed\n");
  867. goto ofld_cmpl_err;
  868. }
  869. }
  870. return;
  871. ofld_cmpl_err:
  872. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  873. wake_up_interruptible(&tgt->ofld_wait);
  874. }
  875. /**
  876. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  877. *
  878. * @hba: adapter structure pointer
  879. * @ofld_kcqe: connection offload kcqe pointer
  880. *
  881. * handle session enable completion, mark the rport as ready
  882. */
  883. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  884. struct fcoe_kcqe *ofld_kcqe)
  885. {
  886. struct bnx2fc_rport *tgt;
  887. u32 conn_id;
  888. u32 context_id;
  889. context_id = ofld_kcqe->fcoe_conn_context_id;
  890. conn_id = ofld_kcqe->fcoe_conn_id;
  891. tgt = hba->tgt_ofld_list[conn_id];
  892. if (!tgt) {
  893. printk(KERN_ALERT PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  894. return;
  895. }
  896. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  897. ofld_kcqe->fcoe_conn_context_id);
  898. /*
  899. * context_id should be the same for this target during offload
  900. * and enable
  901. */
  902. if (tgt->context_id != context_id) {
  903. printk(KERN_ALERT PFX "context id mis-match\n");
  904. return;
  905. }
  906. if (hba != tgt->port->priv) {
  907. printk(KERN_ALERT PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  908. goto enbl_cmpl_err;
  909. }
  910. if (ofld_kcqe->completion_status) {
  911. goto enbl_cmpl_err;
  912. } else {
  913. /* enable successful - rport ready for issuing IOs */
  914. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  915. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  916. wake_up_interruptible(&tgt->ofld_wait);
  917. }
  918. return;
  919. enbl_cmpl_err:
  920. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  921. wake_up_interruptible(&tgt->ofld_wait);
  922. }
  923. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  924. struct fcoe_kcqe *disable_kcqe)
  925. {
  926. struct bnx2fc_rport *tgt;
  927. u32 conn_id;
  928. conn_id = disable_kcqe->fcoe_conn_id;
  929. tgt = hba->tgt_ofld_list[conn_id];
  930. if (!tgt) {
  931. printk(KERN_ALERT PFX "ERROR: disable_cmpl: No disable req\n");
  932. return;
  933. }
  934. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  935. if (disable_kcqe->completion_status) {
  936. printk(KERN_ALERT PFX "ERROR: Disable failed with cmpl status %d\n",
  937. disable_kcqe->completion_status);
  938. return;
  939. } else {
  940. /* disable successful */
  941. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  942. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  943. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  944. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  945. wake_up_interruptible(&tgt->upld_wait);
  946. }
  947. }
  948. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  949. struct fcoe_kcqe *destroy_kcqe)
  950. {
  951. struct bnx2fc_rport *tgt;
  952. u32 conn_id;
  953. conn_id = destroy_kcqe->fcoe_conn_id;
  954. tgt = hba->tgt_ofld_list[conn_id];
  955. if (!tgt) {
  956. printk(KERN_ALERT PFX "destroy_cmpl: No destroy req\n");
  957. return;
  958. }
  959. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  960. if (destroy_kcqe->completion_status) {
  961. printk(KERN_ALERT PFX "Destroy conn failed, cmpl status %d\n",
  962. destroy_kcqe->completion_status);
  963. return;
  964. } else {
  965. /* destroy successful */
  966. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  967. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  968. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  969. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  970. wake_up_interruptible(&tgt->upld_wait);
  971. }
  972. }
  973. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  974. {
  975. switch (err_code) {
  976. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  977. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  978. break;
  979. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  980. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  981. break;
  982. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  983. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  984. break;
  985. default:
  986. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  987. }
  988. }
  989. /**
  990. * bnx2fc_indicae_kcqe - process KCQE
  991. *
  992. * @hba: adapter structure pointer
  993. * @kcqe: kcqe pointer
  994. * @num_cqe: Number of completion queue elements
  995. *
  996. * Generic KCQ event handler
  997. */
  998. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  999. u32 num_cqe)
  1000. {
  1001. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  1002. int i = 0;
  1003. struct fcoe_kcqe *kcqe = NULL;
  1004. while (i < num_cqe) {
  1005. kcqe = (struct fcoe_kcqe *) kcq[i++];
  1006. switch (kcqe->op_code) {
  1007. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  1008. bnx2fc_fastpath_notification(hba, kcqe);
  1009. break;
  1010. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  1011. bnx2fc_process_ofld_cmpl(hba, kcqe);
  1012. break;
  1013. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  1014. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  1015. break;
  1016. case FCOE_KCQE_OPCODE_INIT_FUNC:
  1017. if (kcqe->completion_status !=
  1018. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1019. bnx2fc_init_failure(hba,
  1020. kcqe->completion_status);
  1021. } else {
  1022. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1023. bnx2fc_get_link_state(hba);
  1024. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1025. (u8)hba->pcidev->bus->number);
  1026. }
  1027. break;
  1028. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1029. if (kcqe->completion_status !=
  1030. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1031. printk(KERN_ERR PFX "DESTROY failed\n");
  1032. } else {
  1033. printk(KERN_ERR PFX "DESTROY success\n");
  1034. }
  1035. hba->flags |= BNX2FC_FLAG_DESTROY_CMPL;
  1036. wake_up_interruptible(&hba->destroy_wait);
  1037. break;
  1038. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1039. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1040. break;
  1041. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1042. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1043. break;
  1044. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1045. if (kcqe->completion_status !=
  1046. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1047. printk(KERN_ERR PFX "STAT failed\n");
  1048. complete(&hba->stat_req_done);
  1049. break;
  1050. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1051. /* fall thru */
  1052. default:
  1053. printk(KERN_ALERT PFX "unknown opcode 0x%x\n",
  1054. kcqe->op_code);
  1055. }
  1056. }
  1057. }
  1058. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1059. {
  1060. struct fcoe_sqe *sqe;
  1061. sqe = &tgt->sq[tgt->sq_prod_idx];
  1062. /* Fill SQ WQE */
  1063. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1064. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1065. /* Advance SQ Prod Idx */
  1066. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1067. tgt->sq_prod_idx = 0;
  1068. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1069. }
  1070. }
  1071. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1072. {
  1073. struct b577xx_doorbell_set_prod ev_doorbell;
  1074. u32 msg;
  1075. wmb();
  1076. memset(&ev_doorbell, 0, sizeof(struct b577xx_doorbell_set_prod));
  1077. ev_doorbell.header.header = B577XX_DOORBELL_HDR_DB_TYPE;
  1078. ev_doorbell.prod = tgt->sq_prod_idx |
  1079. (tgt->sq_curr_toggle_bit << 15);
  1080. ev_doorbell.header.header |= B577XX_FCOE_CONNECTION_TYPE <<
  1081. B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT;
  1082. msg = *((u32 *)&ev_doorbell);
  1083. writel(cpu_to_le32(msg), tgt->ctx_base);
  1084. mmiowb();
  1085. }
  1086. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1087. {
  1088. u32 context_id = tgt->context_id;
  1089. struct fcoe_port *port = tgt->port;
  1090. u32 reg_off;
  1091. resource_size_t reg_base;
  1092. struct bnx2fc_hba *hba = port->priv;
  1093. reg_base = pci_resource_start(hba->pcidev,
  1094. BNX2X_DOORBELL_PCI_BAR);
  1095. reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
  1096. (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
  1097. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1098. if (!tgt->ctx_base)
  1099. return -ENOMEM;
  1100. return 0;
  1101. }
  1102. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1103. {
  1104. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1105. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1106. return NULL;
  1107. tgt->rq_cons_idx += num_items;
  1108. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1109. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1110. return buf;
  1111. }
  1112. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1113. {
  1114. /* return the rq buffer */
  1115. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1116. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1117. /* Wrap around RQ */
  1118. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1119. }
  1120. tgt->rq_prod_idx = next_prod_idx;
  1121. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1122. }
  1123. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1124. struct fcoe_task_ctx_entry *task,
  1125. u16 orig_xid)
  1126. {
  1127. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1128. struct bnx2fc_rport *tgt = io_req->tgt;
  1129. u32 context_id = tgt->context_id;
  1130. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1131. /* Tx Write Rx Read */
  1132. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1133. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1134. task->tx_wr_rx_rd.init_flags = task_type <<
  1135. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1136. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1137. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1138. /* Common */
  1139. task->cmn.common_flags = context_id <<
  1140. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1141. task->cmn.general.cleanup_info.task_id = orig_xid;
  1142. }
  1143. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1144. struct fcoe_task_ctx_entry *task)
  1145. {
  1146. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1147. struct bnx2fc_rport *tgt = io_req->tgt;
  1148. struct fc_frame_header *fc_hdr;
  1149. u8 task_type = 0;
  1150. u64 *hdr;
  1151. u64 temp_hdr[3];
  1152. u32 context_id;
  1153. /* Obtain task_type */
  1154. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1155. (io_req->cmd_type == BNX2FC_ELS)) {
  1156. task_type = FCOE_TASK_TYPE_MIDPATH;
  1157. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1158. task_type = FCOE_TASK_TYPE_ABTS;
  1159. }
  1160. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1161. /* Setup the task from io_req for easy reference */
  1162. io_req->task = task;
  1163. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1164. io_req->cmd_type, task_type);
  1165. /* Tx only */
  1166. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1167. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1168. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1169. (u32)mp_req->mp_req_bd_dma;
  1170. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1171. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1172. task->tx_wr_only.sgl_ctx.mul_sges.sgl_size = 1;
  1173. BNX2FC_IO_DBG(io_req, "init_mp_task - bd_dma = 0x%llx\n",
  1174. (unsigned long long)mp_req->mp_req_bd_dma);
  1175. }
  1176. /* Tx Write Rx Read */
  1177. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1178. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1179. task->tx_wr_rx_rd.init_flags = task_type <<
  1180. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1181. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_DEV_TYPE_DISK <<
  1182. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT;
  1183. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1184. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1185. /* Common */
  1186. task->cmn.data_2_trns = io_req->data_xfer_len;
  1187. context_id = tgt->context_id;
  1188. task->cmn.common_flags = context_id <<
  1189. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1190. task->cmn.common_flags |= 1 <<
  1191. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT;
  1192. task->cmn.common_flags |= 1 <<
  1193. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT;
  1194. /* Rx Write Tx Read */
  1195. fc_hdr = &(mp_req->req_fc_hdr);
  1196. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1197. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1198. fc_hdr->fh_rx_id = htons(0xffff);
  1199. task->rx_wr_tx_rd.rx_id = 0xffff;
  1200. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1201. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1202. }
  1203. /* Fill FC Header into middle path buffer */
  1204. hdr = (u64 *) &task->cmn.general.cmd_info.mp_fc_frame.fc_hdr;
  1205. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1206. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1207. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1208. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1209. /* Rx Only */
  1210. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1211. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1212. (u32)mp_req->mp_resp_bd_dma;
  1213. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1214. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1215. task->rx_wr_only.sgl_ctx.mul_sges.sgl_size = 1;
  1216. }
  1217. }
  1218. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1219. struct fcoe_task_ctx_entry *task)
  1220. {
  1221. u8 task_type;
  1222. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1223. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1224. struct bnx2fc_rport *tgt = io_req->tgt;
  1225. u64 *fcp_cmnd;
  1226. u64 tmp_fcp_cmnd[4];
  1227. u32 context_id;
  1228. int cnt, i;
  1229. int bd_count;
  1230. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1231. /* Setup the task from io_req for easy reference */
  1232. io_req->task = task;
  1233. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1234. task_type = FCOE_TASK_TYPE_WRITE;
  1235. else
  1236. task_type = FCOE_TASK_TYPE_READ;
  1237. /* Tx only */
  1238. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1239. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1240. (u32)bd_tbl->bd_tbl_dma;
  1241. task->tx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1242. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1243. task->tx_wr_only.sgl_ctx.mul_sges.sgl_size =
  1244. bd_tbl->bd_valid;
  1245. }
  1246. /*Tx Write Rx Read */
  1247. /* Init state to NORMAL */
  1248. task->tx_wr_rx_rd.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1249. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT;
  1250. task->tx_wr_rx_rd.init_flags = task_type <<
  1251. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT;
  1252. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_DEV_TYPE_DISK <<
  1253. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT;
  1254. task->tx_wr_rx_rd.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1255. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT;
  1256. /* Common */
  1257. task->cmn.data_2_trns = io_req->data_xfer_len;
  1258. context_id = tgt->context_id;
  1259. task->cmn.common_flags = context_id <<
  1260. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT;
  1261. task->cmn.common_flags |= 1 <<
  1262. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT;
  1263. task->cmn.common_flags |= 1 <<
  1264. FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT;
  1265. /* Set initiative ownership */
  1266. task->cmn.common_flags |= FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT;
  1267. /* Set initial seq counter */
  1268. task->cmn.tx_low_seq_cnt = 1;
  1269. /* Set state to "waiting for the first packet" */
  1270. task->cmn.common_flags |= FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME;
  1271. /* Fill FCP_CMND IU */
  1272. fcp_cmnd = (u64 *)
  1273. task->cmn.general.cmd_info.fcp_cmd_payload.opaque;
  1274. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1275. /* swap fcp_cmnd */
  1276. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1277. for (i = 0; i < cnt; i++) {
  1278. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1279. fcp_cmnd++;
  1280. }
  1281. /* Rx Write Tx Read */
  1282. task->rx_wr_tx_rd.rx_id = 0xffff;
  1283. /* Rx Only */
  1284. if (task_type == FCOE_TASK_TYPE_READ) {
  1285. bd_count = bd_tbl->bd_valid;
  1286. if (bd_count == 1) {
  1287. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1288. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_addr.lo =
  1289. fcoe_bd_tbl->buf_addr_lo;
  1290. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_addr.hi =
  1291. fcoe_bd_tbl->buf_addr_hi;
  1292. task->rx_wr_only.sgl_ctx.single_sge.cur_buf_rem =
  1293. fcoe_bd_tbl->buf_len;
  1294. task->tx_wr_rx_rd.init_flags |= 1 <<
  1295. FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT;
  1296. } else {
  1297. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.lo =
  1298. (u32)bd_tbl->bd_tbl_dma;
  1299. task->rx_wr_only.sgl_ctx.mul_sges.cur_sge_addr.hi =
  1300. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1301. task->rx_wr_only.sgl_ctx.mul_sges.sgl_size =
  1302. bd_tbl->bd_valid;
  1303. }
  1304. }
  1305. }
  1306. /**
  1307. * bnx2fc_setup_task_ctx - allocate and map task context
  1308. *
  1309. * @hba: pointer to adapter structure
  1310. *
  1311. * allocate memory for task context, and associated BD table to be used
  1312. * by firmware
  1313. *
  1314. */
  1315. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1316. {
  1317. int rc = 0;
  1318. struct regpair *task_ctx_bdt;
  1319. dma_addr_t addr;
  1320. int i;
  1321. /*
  1322. * Allocate task context bd table. A page size of bd table
  1323. * can map 256 buffers. Each buffer contains 32 task context
  1324. * entries. Hence the limit with one page is 8192 task context
  1325. * entries.
  1326. */
  1327. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1328. PAGE_SIZE,
  1329. &hba->task_ctx_bd_dma,
  1330. GFP_KERNEL);
  1331. if (!hba->task_ctx_bd_tbl) {
  1332. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1333. rc = -1;
  1334. goto out;
  1335. }
  1336. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1337. /*
  1338. * Allocate task_ctx which is an array of pointers pointing to
  1339. * a page containing 32 task contexts
  1340. */
  1341. hba->task_ctx = kzalloc((BNX2FC_TASK_CTX_ARR_SZ * sizeof(void *)),
  1342. GFP_KERNEL);
  1343. if (!hba->task_ctx) {
  1344. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1345. rc = -1;
  1346. goto out1;
  1347. }
  1348. /*
  1349. * Allocate task_ctx_dma which is an array of dma addresses
  1350. */
  1351. hba->task_ctx_dma = kmalloc((BNX2FC_TASK_CTX_ARR_SZ *
  1352. sizeof(dma_addr_t)), GFP_KERNEL);
  1353. if (!hba->task_ctx_dma) {
  1354. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1355. rc = -1;
  1356. goto out2;
  1357. }
  1358. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1359. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1360. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1361. PAGE_SIZE,
  1362. &hba->task_ctx_dma[i],
  1363. GFP_KERNEL);
  1364. if (!hba->task_ctx[i]) {
  1365. printk(KERN_ERR PFX "unable to alloc task context\n");
  1366. rc = -1;
  1367. goto out3;
  1368. }
  1369. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1370. addr = (u64)hba->task_ctx_dma[i];
  1371. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1372. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1373. task_ctx_bdt++;
  1374. }
  1375. return 0;
  1376. out3:
  1377. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1378. if (hba->task_ctx[i]) {
  1379. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1380. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1381. hba->task_ctx[i] = NULL;
  1382. }
  1383. }
  1384. kfree(hba->task_ctx_dma);
  1385. hba->task_ctx_dma = NULL;
  1386. out2:
  1387. kfree(hba->task_ctx);
  1388. hba->task_ctx = NULL;
  1389. out1:
  1390. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1391. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1392. hba->task_ctx_bd_tbl = NULL;
  1393. out:
  1394. return rc;
  1395. }
  1396. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1397. {
  1398. int i;
  1399. if (hba->task_ctx_bd_tbl) {
  1400. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1401. hba->task_ctx_bd_tbl,
  1402. hba->task_ctx_bd_dma);
  1403. hba->task_ctx_bd_tbl = NULL;
  1404. }
  1405. if (hba->task_ctx) {
  1406. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1407. if (hba->task_ctx[i]) {
  1408. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1409. hba->task_ctx[i],
  1410. hba->task_ctx_dma[i]);
  1411. hba->task_ctx[i] = NULL;
  1412. }
  1413. }
  1414. kfree(hba->task_ctx);
  1415. hba->task_ctx = NULL;
  1416. }
  1417. kfree(hba->task_ctx_dma);
  1418. hba->task_ctx_dma = NULL;
  1419. }
  1420. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1421. {
  1422. int i;
  1423. int segment_count;
  1424. int hash_table_size;
  1425. u32 *pbl;
  1426. segment_count = hba->hash_tbl_segment_count;
  1427. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1428. sizeof(struct fcoe_hash_table_entry);
  1429. pbl = hba->hash_tbl_pbl;
  1430. for (i = 0; i < segment_count; ++i) {
  1431. dma_addr_t dma_address;
  1432. dma_address = le32_to_cpu(*pbl);
  1433. ++pbl;
  1434. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1435. ++pbl;
  1436. dma_free_coherent(&hba->pcidev->dev,
  1437. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1438. hba->hash_tbl_segments[i],
  1439. dma_address);
  1440. }
  1441. if (hba->hash_tbl_pbl) {
  1442. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1443. hba->hash_tbl_pbl,
  1444. hba->hash_tbl_pbl_dma);
  1445. hba->hash_tbl_pbl = NULL;
  1446. }
  1447. }
  1448. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1449. {
  1450. int i;
  1451. int hash_table_size;
  1452. int segment_count;
  1453. int segment_array_size;
  1454. int dma_segment_array_size;
  1455. dma_addr_t *dma_segment_array;
  1456. u32 *pbl;
  1457. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1458. sizeof(struct fcoe_hash_table_entry);
  1459. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1460. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1461. hba->hash_tbl_segment_count = segment_count;
  1462. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1463. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1464. if (!hba->hash_tbl_segments) {
  1465. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1466. return -ENOMEM;
  1467. }
  1468. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1469. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1470. if (!dma_segment_array) {
  1471. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1472. return -ENOMEM;
  1473. }
  1474. for (i = 0; i < segment_count; ++i) {
  1475. hba->hash_tbl_segments[i] =
  1476. dma_alloc_coherent(&hba->pcidev->dev,
  1477. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1478. &dma_segment_array[i],
  1479. GFP_KERNEL);
  1480. if (!hba->hash_tbl_segments[i]) {
  1481. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1482. while (--i >= 0) {
  1483. dma_free_coherent(&hba->pcidev->dev,
  1484. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1485. hba->hash_tbl_segments[i],
  1486. dma_segment_array[i]);
  1487. hba->hash_tbl_segments[i] = NULL;
  1488. }
  1489. kfree(dma_segment_array);
  1490. return -ENOMEM;
  1491. }
  1492. memset(hba->hash_tbl_segments[i], 0,
  1493. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1494. }
  1495. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1496. PAGE_SIZE,
  1497. &hba->hash_tbl_pbl_dma,
  1498. GFP_KERNEL);
  1499. if (!hba->hash_tbl_pbl) {
  1500. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1501. kfree(dma_segment_array);
  1502. return -ENOMEM;
  1503. }
  1504. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1505. pbl = hba->hash_tbl_pbl;
  1506. for (i = 0; i < segment_count; ++i) {
  1507. u64 paddr = dma_segment_array[i];
  1508. *pbl = cpu_to_le32((u32) paddr);
  1509. ++pbl;
  1510. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1511. ++pbl;
  1512. }
  1513. pbl = hba->hash_tbl_pbl;
  1514. i = 0;
  1515. while (*pbl && *(pbl + 1)) {
  1516. u32 lo;
  1517. u32 hi;
  1518. lo = *pbl;
  1519. ++pbl;
  1520. hi = *pbl;
  1521. ++pbl;
  1522. ++i;
  1523. }
  1524. kfree(dma_segment_array);
  1525. return 0;
  1526. }
  1527. /**
  1528. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1529. *
  1530. * @hba: Pointer to adapter structure
  1531. *
  1532. */
  1533. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1534. {
  1535. u64 addr;
  1536. u32 mem_size;
  1537. int i;
  1538. if (bnx2fc_allocate_hash_table(hba))
  1539. return -ENOMEM;
  1540. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1541. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1542. &hba->t2_hash_tbl_ptr_dma,
  1543. GFP_KERNEL);
  1544. if (!hba->t2_hash_tbl_ptr) {
  1545. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1546. bnx2fc_free_fw_resc(hba);
  1547. return -ENOMEM;
  1548. }
  1549. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1550. mem_size = BNX2FC_NUM_MAX_SESS *
  1551. sizeof(struct fcoe_t2_hash_table_entry);
  1552. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1553. &hba->t2_hash_tbl_dma,
  1554. GFP_KERNEL);
  1555. if (!hba->t2_hash_tbl) {
  1556. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1557. bnx2fc_free_fw_resc(hba);
  1558. return -ENOMEM;
  1559. }
  1560. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1561. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1562. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1563. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1564. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1565. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1566. }
  1567. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1568. PAGE_SIZE, &hba->dummy_buf_dma,
  1569. GFP_KERNEL);
  1570. if (!hba->dummy_buffer) {
  1571. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1572. bnx2fc_free_fw_resc(hba);
  1573. return -ENOMEM;
  1574. }
  1575. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1576. PAGE_SIZE,
  1577. &hba->stats_buf_dma,
  1578. GFP_KERNEL);
  1579. if (!hba->stats_buffer) {
  1580. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1581. bnx2fc_free_fw_resc(hba);
  1582. return -ENOMEM;
  1583. }
  1584. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1585. return 0;
  1586. }
  1587. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1588. {
  1589. u32 mem_size;
  1590. if (hba->stats_buffer) {
  1591. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1592. hba->stats_buffer, hba->stats_buf_dma);
  1593. hba->stats_buffer = NULL;
  1594. }
  1595. if (hba->dummy_buffer) {
  1596. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1597. hba->dummy_buffer, hba->dummy_buf_dma);
  1598. hba->dummy_buffer = NULL;
  1599. }
  1600. if (hba->t2_hash_tbl_ptr) {
  1601. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1602. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1603. hba->t2_hash_tbl_ptr,
  1604. hba->t2_hash_tbl_ptr_dma);
  1605. hba->t2_hash_tbl_ptr = NULL;
  1606. }
  1607. if (hba->t2_hash_tbl) {
  1608. mem_size = BNX2FC_NUM_MAX_SESS *
  1609. sizeof(struct fcoe_t2_hash_table_entry);
  1610. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1611. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1612. hba->t2_hash_tbl = NULL;
  1613. }
  1614. bnx2fc_free_hash_table(hba);
  1615. }