mcdi.c 31 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192
  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. /* Software-defined structure to the shared-memory */
  23. #define CMD_NOTIFY_PORT0 0
  24. #define CMD_NOTIFY_PORT1 4
  25. #define CMD_PDU_PORT0 0x008
  26. #define CMD_PDU_PORT1 0x108
  27. #define REBOOT_FLAG_PORT0 0x3f8
  28. #define REBOOT_FLAG_PORT1 0x3fc
  29. #define MCDI_RPC_TIMEOUT 10 /*seconds */
  30. #define MCDI_PDU(efx) \
  31. (efx_port_num(efx) ? CMD_PDU_PORT1 : CMD_PDU_PORT0)
  32. #define MCDI_DOORBELL(efx) \
  33. (efx_port_num(efx) ? CMD_NOTIFY_PORT1 : CMD_NOTIFY_PORT0)
  34. #define MCDI_REBOOT_FLAG(efx) \
  35. (efx_port_num(efx) ? REBOOT_FLAG_PORT1 : REBOOT_FLAG_PORT0)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. void efx_mcdi_init(struct efx_nic *efx)
  46. {
  47. struct efx_mcdi_iface *mcdi;
  48. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  49. return;
  50. mcdi = efx_mcdi(efx);
  51. init_waitqueue_head(&mcdi->wq);
  52. spin_lock_init(&mcdi->iface_lock);
  53. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  54. mcdi->mode = MCDI_MODE_POLL;
  55. (void) efx_mcdi_poll_reboot(efx);
  56. }
  57. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  58. const u8 *inbuf, size_t inlen)
  59. {
  60. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  61. unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  62. unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
  63. unsigned int i;
  64. efx_dword_t hdr;
  65. u32 xflags, seqno;
  66. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  67. BUG_ON(inlen & 3 || inlen >= 0x100);
  68. seqno = mcdi->seqno & SEQ_MASK;
  69. xflags = 0;
  70. if (mcdi->mode == MCDI_MODE_EVENTS)
  71. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  72. EFX_POPULATE_DWORD_6(hdr,
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. efx_writed(efx, &hdr, pdu);
  80. for (i = 0; i < inlen; i += 4)
  81. _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
  82. /* Ensure the payload is written out before the header */
  83. wmb();
  84. /* ring the doorbell with a distinctive value */
  85. _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
  86. }
  87. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  88. {
  89. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  90. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  91. int i;
  92. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  93. BUG_ON(outlen & 3 || outlen >= 0x100);
  94. for (i = 0; i < outlen; i += 4)
  95. *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
  96. }
  97. static int efx_mcdi_poll(struct efx_nic *efx)
  98. {
  99. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  100. unsigned int time, finish;
  101. unsigned int respseq, respcmd, error;
  102. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  103. unsigned int rc, spins;
  104. efx_dword_t reg;
  105. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  106. rc = -efx_mcdi_poll_reboot(efx);
  107. if (rc)
  108. goto out;
  109. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  110. * because generally mcdi responses are fast. After that, back off
  111. * and poll once a jiffy (approximately)
  112. */
  113. spins = TICK_USEC;
  114. finish = get_seconds() + MCDI_RPC_TIMEOUT;
  115. while (1) {
  116. if (spins != 0) {
  117. --spins;
  118. udelay(1);
  119. } else {
  120. schedule_timeout_uninterruptible(1);
  121. }
  122. time = get_seconds();
  123. rmb();
  124. efx_readd(efx, &reg, pdu);
  125. /* All 1's indicates that shared memory is in reset (and is
  126. * not a valid header). Wait for it to come out reset before
  127. * completing the command */
  128. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  129. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  130. break;
  131. if (time >= finish)
  132. return -ETIMEDOUT;
  133. }
  134. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  135. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  136. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  137. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  138. if (error && mcdi->resplen == 0) {
  139. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  140. rc = EIO;
  141. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  142. netif_err(efx, hw, efx->net_dev,
  143. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  144. respseq, mcdi->seqno);
  145. rc = EIO;
  146. } else if (error) {
  147. efx_readd(efx, &reg, pdu + 4);
  148. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  149. #define TRANSLATE_ERROR(name) \
  150. case MC_CMD_ERR_ ## name: \
  151. rc = name; \
  152. break
  153. TRANSLATE_ERROR(ENOENT);
  154. TRANSLATE_ERROR(EINTR);
  155. TRANSLATE_ERROR(EACCES);
  156. TRANSLATE_ERROR(EBUSY);
  157. TRANSLATE_ERROR(EINVAL);
  158. TRANSLATE_ERROR(EDEADLK);
  159. TRANSLATE_ERROR(ENOSYS);
  160. TRANSLATE_ERROR(ETIME);
  161. #undef TRANSLATE_ERROR
  162. default:
  163. rc = EIO;
  164. break;
  165. }
  166. } else
  167. rc = 0;
  168. out:
  169. mcdi->resprc = rc;
  170. if (rc)
  171. mcdi->resplen = 0;
  172. /* Return rc=0 like wait_event_timeout() */
  173. return 0;
  174. }
  175. /* Test and clear MC-rebooted flag for this port/function */
  176. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  177. {
  178. unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx);
  179. efx_dword_t reg;
  180. uint32_t value;
  181. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  182. return false;
  183. efx_readd(efx, &reg, addr);
  184. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  185. if (value == 0)
  186. return 0;
  187. EFX_ZERO_DWORD(reg);
  188. efx_writed(efx, &reg, addr);
  189. if (value == MC_STATUS_DWORD_ASSERT)
  190. return -EINTR;
  191. else
  192. return -EIO;
  193. }
  194. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  195. {
  196. /* Wait until the interface becomes QUIESCENT and we win the race
  197. * to mark it RUNNING. */
  198. wait_event(mcdi->wq,
  199. atomic_cmpxchg(&mcdi->state,
  200. MCDI_STATE_QUIESCENT,
  201. MCDI_STATE_RUNNING)
  202. == MCDI_STATE_QUIESCENT);
  203. }
  204. static int efx_mcdi_await_completion(struct efx_nic *efx)
  205. {
  206. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  207. if (wait_event_timeout(
  208. mcdi->wq,
  209. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  210. msecs_to_jiffies(MCDI_RPC_TIMEOUT * 1000)) == 0)
  211. return -ETIMEDOUT;
  212. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  213. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  214. * completed the request first, then we'll just end up completing the
  215. * request again, which is safe.
  216. *
  217. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  218. * wait_event_timeout() implicitly provides.
  219. */
  220. if (mcdi->mode == MCDI_MODE_POLL)
  221. return efx_mcdi_poll(efx);
  222. return 0;
  223. }
  224. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  225. {
  226. /* If the interface is RUNNING, then move to COMPLETED and wake any
  227. * waiters. If the interface isn't in RUNNING then we've received a
  228. * duplicate completion after we've already transitioned back to
  229. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  230. * have failed the seqno check].
  231. */
  232. if (atomic_cmpxchg(&mcdi->state,
  233. MCDI_STATE_RUNNING,
  234. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  235. wake_up(&mcdi->wq);
  236. return true;
  237. }
  238. return false;
  239. }
  240. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  241. {
  242. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  243. wake_up(&mcdi->wq);
  244. }
  245. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  246. unsigned int datalen, unsigned int errno)
  247. {
  248. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  249. bool wake = false;
  250. spin_lock(&mcdi->iface_lock);
  251. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  252. if (mcdi->credits)
  253. /* The request has been cancelled */
  254. --mcdi->credits;
  255. else
  256. netif_err(efx, hw, efx->net_dev,
  257. "MC response mismatch tx seq 0x%x rx "
  258. "seq 0x%x\n", seqno, mcdi->seqno);
  259. } else {
  260. mcdi->resprc = errno;
  261. mcdi->resplen = datalen;
  262. wake = true;
  263. }
  264. spin_unlock(&mcdi->iface_lock);
  265. if (wake)
  266. efx_mcdi_complete(mcdi);
  267. }
  268. /* Issue the given command by writing the data into the shared memory PDU,
  269. * ring the doorbell and wait for completion. Copyout the result. */
  270. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  271. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  272. size_t *outlen_actual)
  273. {
  274. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  275. int rc;
  276. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  277. efx_mcdi_acquire(mcdi);
  278. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  279. spin_lock_bh(&mcdi->iface_lock);
  280. ++mcdi->seqno;
  281. spin_unlock_bh(&mcdi->iface_lock);
  282. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  283. if (mcdi->mode == MCDI_MODE_POLL)
  284. rc = efx_mcdi_poll(efx);
  285. else
  286. rc = efx_mcdi_await_completion(efx);
  287. if (rc != 0) {
  288. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  289. * and completing a request we've just cancelled, by ensuring
  290. * that the seqno check therein fails.
  291. */
  292. spin_lock_bh(&mcdi->iface_lock);
  293. ++mcdi->seqno;
  294. ++mcdi->credits;
  295. spin_unlock_bh(&mcdi->iface_lock);
  296. netif_err(efx, hw, efx->net_dev,
  297. "MC command 0x%x inlen %d mode %d timed out\n",
  298. cmd, (int)inlen, mcdi->mode);
  299. } else {
  300. size_t resplen;
  301. /* At the very least we need a memory barrier here to ensure
  302. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  303. * a spurious efx_mcdi_ev_cpl() running concurrently by
  304. * acquiring the iface_lock. */
  305. spin_lock_bh(&mcdi->iface_lock);
  306. rc = -mcdi->resprc;
  307. resplen = mcdi->resplen;
  308. spin_unlock_bh(&mcdi->iface_lock);
  309. if (rc == 0) {
  310. efx_mcdi_copyout(efx, outbuf,
  311. min(outlen, mcdi->resplen + 3) & ~0x3);
  312. if (outlen_actual != NULL)
  313. *outlen_actual = resplen;
  314. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  315. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  316. else if (rc == -EIO || rc == -EINTR) {
  317. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  318. -rc);
  319. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  320. } else
  321. netif_dbg(efx, hw, efx->net_dev,
  322. "MC command 0x%x inlen %d failed rc=%d\n",
  323. cmd, (int)inlen, -rc);
  324. }
  325. efx_mcdi_release(mcdi);
  326. return rc;
  327. }
  328. void efx_mcdi_mode_poll(struct efx_nic *efx)
  329. {
  330. struct efx_mcdi_iface *mcdi;
  331. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  332. return;
  333. mcdi = efx_mcdi(efx);
  334. if (mcdi->mode == MCDI_MODE_POLL)
  335. return;
  336. /* We can switch from event completion to polled completion, because
  337. * mcdi requests are always completed in shared memory. We do this by
  338. * switching the mode to POLL'd then completing the request.
  339. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  340. *
  341. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  342. * which efx_mcdi_complete() provides for us.
  343. */
  344. mcdi->mode = MCDI_MODE_POLL;
  345. efx_mcdi_complete(mcdi);
  346. }
  347. void efx_mcdi_mode_event(struct efx_nic *efx)
  348. {
  349. struct efx_mcdi_iface *mcdi;
  350. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  351. return;
  352. mcdi = efx_mcdi(efx);
  353. if (mcdi->mode == MCDI_MODE_EVENTS)
  354. return;
  355. /* We can't switch from polled to event completion in the middle of a
  356. * request, because the completion method is specified in the request.
  357. * So acquire the interface to serialise the requestors. We don't need
  358. * to acquire the iface_lock to change the mode here, but we do need a
  359. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  360. * efx_mcdi_acquire() provides.
  361. */
  362. efx_mcdi_acquire(mcdi);
  363. mcdi->mode = MCDI_MODE_EVENTS;
  364. efx_mcdi_release(mcdi);
  365. }
  366. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  367. {
  368. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  369. /* If there is an outstanding MCDI request, it has been terminated
  370. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  371. * in polled mode, then do nothing because the MC reboot handler will
  372. * set the header correctly. However, if the mcdi interface is waiting
  373. * for a CMDDONE event it won't receive it [and since all MCDI events
  374. * are sent to the same queue, we can't be racing with
  375. * efx_mcdi_ev_cpl()]
  376. *
  377. * There's a race here with efx_mcdi_rpc(), because we might receive
  378. * a REBOOT event *before* the request has been copied out. In polled
  379. * mode (during startup) this is irrelevant, because efx_mcdi_complete()
  380. * is ignored. In event mode, this condition is just an edge-case of
  381. * receiving a REBOOT event after posting the MCDI request. Did the mc
  382. * reboot before or after the copyout? The best we can do always is
  383. * just return failure.
  384. */
  385. spin_lock(&mcdi->iface_lock);
  386. if (efx_mcdi_complete(mcdi)) {
  387. if (mcdi->mode == MCDI_MODE_EVENTS) {
  388. mcdi->resprc = rc;
  389. mcdi->resplen = 0;
  390. ++mcdi->credits;
  391. }
  392. } else
  393. /* Nobody was waiting for an MCDI request, so trigger a reset */
  394. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  395. spin_unlock(&mcdi->iface_lock);
  396. }
  397. static unsigned int efx_mcdi_event_link_speed[] = {
  398. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  399. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  400. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  401. };
  402. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  403. {
  404. u32 flags, fcntl, speed, lpa;
  405. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  406. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  407. speed = efx_mcdi_event_link_speed[speed];
  408. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  409. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  410. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  411. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  412. * which is only run after flushing the event queues. Therefore, it
  413. * is safe to modify the link state outside of the mac_lock here.
  414. */
  415. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  416. efx_mcdi_phy_check_fcntl(efx, lpa);
  417. efx_link_status_changed(efx);
  418. }
  419. static const char *sensor_names[] = {
  420. [MC_CMD_SENSOR_CONTROLLER_TEMP] = "Controller temp. sensor",
  421. [MC_CMD_SENSOR_PHY_COMMON_TEMP] = "PHY shared temp. sensor",
  422. [MC_CMD_SENSOR_CONTROLLER_COOLING] = "Controller cooling",
  423. [MC_CMD_SENSOR_PHY0_TEMP] = "PHY 0 temp. sensor",
  424. [MC_CMD_SENSOR_PHY0_COOLING] = "PHY 0 cooling",
  425. [MC_CMD_SENSOR_PHY1_TEMP] = "PHY 1 temp. sensor",
  426. [MC_CMD_SENSOR_PHY1_COOLING] = "PHY 1 cooling",
  427. [MC_CMD_SENSOR_IN_1V0] = "1.0V supply sensor",
  428. [MC_CMD_SENSOR_IN_1V2] = "1.2V supply sensor",
  429. [MC_CMD_SENSOR_IN_1V8] = "1.8V supply sensor",
  430. [MC_CMD_SENSOR_IN_2V5] = "2.5V supply sensor",
  431. [MC_CMD_SENSOR_IN_3V3] = "3.3V supply sensor",
  432. [MC_CMD_SENSOR_IN_12V0] = "12V supply sensor"
  433. };
  434. static const char *sensor_status_names[] = {
  435. [MC_CMD_SENSOR_STATE_OK] = "OK",
  436. [MC_CMD_SENSOR_STATE_WARNING] = "Warning",
  437. [MC_CMD_SENSOR_STATE_FATAL] = "Fatal",
  438. [MC_CMD_SENSOR_STATE_BROKEN] = "Device failure",
  439. };
  440. static void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
  441. {
  442. unsigned int monitor, state, value;
  443. const char *name, *state_txt;
  444. monitor = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_MONITOR);
  445. state = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_STATE);
  446. value = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_VALUE);
  447. /* Deal gracefully with the board having more drivers than we
  448. * know about, but do not expect new sensor states. */
  449. name = (monitor >= ARRAY_SIZE(sensor_names))
  450. ? "No sensor name available" :
  451. sensor_names[monitor];
  452. EFX_BUG_ON_PARANOID(state >= ARRAY_SIZE(sensor_status_names));
  453. state_txt = sensor_status_names[state];
  454. netif_err(efx, hw, efx->net_dev,
  455. "Sensor %d (%s) reports condition '%s' for raw value %d\n",
  456. monitor, name, state_txt, value);
  457. }
  458. /* Called from falcon_process_eventq for MCDI events */
  459. void efx_mcdi_process_event(struct efx_channel *channel,
  460. efx_qword_t *event)
  461. {
  462. struct efx_nic *efx = channel->efx;
  463. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  464. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  465. switch (code) {
  466. case MCDI_EVENT_CODE_BADSSERT:
  467. netif_err(efx, hw, efx->net_dev,
  468. "MC watchdog or assertion failure at 0x%x\n", data);
  469. efx_mcdi_ev_death(efx, EINTR);
  470. break;
  471. case MCDI_EVENT_CODE_PMNOTICE:
  472. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  473. break;
  474. case MCDI_EVENT_CODE_CMDDONE:
  475. efx_mcdi_ev_cpl(efx,
  476. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  477. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  478. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  479. break;
  480. case MCDI_EVENT_CODE_LINKCHANGE:
  481. efx_mcdi_process_link_change(efx, event);
  482. break;
  483. case MCDI_EVENT_CODE_SENSOREVT:
  484. efx_mcdi_sensor_event(efx, event);
  485. break;
  486. case MCDI_EVENT_CODE_SCHEDERR:
  487. netif_info(efx, hw, efx->net_dev,
  488. "MC Scheduler error address=0x%x\n", data);
  489. break;
  490. case MCDI_EVENT_CODE_REBOOT:
  491. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  492. efx_mcdi_ev_death(efx, EIO);
  493. break;
  494. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  495. /* MAC stats are gather lazily. We can ignore this. */
  496. break;
  497. default:
  498. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  499. code);
  500. }
  501. }
  502. /**************************************************************************
  503. *
  504. * Specific request functions
  505. *
  506. **************************************************************************
  507. */
  508. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  509. {
  510. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_V1_OUT_LEN, 4)];
  511. size_t outlength;
  512. const __le16 *ver_words;
  513. int rc;
  514. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  515. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  516. outbuf, sizeof(outbuf), &outlength);
  517. if (rc)
  518. goto fail;
  519. if (outlength < MC_CMD_GET_VERSION_V1_OUT_LEN) {
  520. rc = -EIO;
  521. goto fail;
  522. }
  523. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  524. snprintf(buf, len, "%u.%u.%u.%u",
  525. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  526. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  527. return;
  528. fail:
  529. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  530. buf[0] = 0;
  531. }
  532. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  533. bool *was_attached)
  534. {
  535. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  536. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  537. size_t outlen;
  538. int rc;
  539. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  540. driver_operating ? 1 : 0);
  541. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  542. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  543. outbuf, sizeof(outbuf), &outlen);
  544. if (rc)
  545. goto fail;
  546. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  547. rc = -EIO;
  548. goto fail;
  549. }
  550. if (was_attached != NULL)
  551. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  552. return 0;
  553. fail:
  554. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  555. return rc;
  556. }
  557. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  558. u16 *fw_subtype_list)
  559. {
  560. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LEN];
  561. size_t outlen;
  562. int port_num = efx_port_num(efx);
  563. int offset;
  564. int rc;
  565. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  566. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  567. outbuf, sizeof(outbuf), &outlen);
  568. if (rc)
  569. goto fail;
  570. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LEN) {
  571. rc = -EIO;
  572. goto fail;
  573. }
  574. offset = (port_num)
  575. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  576. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  577. if (mac_address)
  578. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  579. if (fw_subtype_list)
  580. memcpy(fw_subtype_list,
  581. outbuf + MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST,
  582. MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN);
  583. return 0;
  584. fail:
  585. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  586. __func__, rc, (int)outlen);
  587. return rc;
  588. }
  589. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  590. {
  591. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  592. u32 dest = 0;
  593. int rc;
  594. if (uart)
  595. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  596. if (evq)
  597. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  598. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  599. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  600. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  601. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  602. NULL, 0, NULL);
  603. if (rc)
  604. goto fail;
  605. return 0;
  606. fail:
  607. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  608. return rc;
  609. }
  610. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  611. {
  612. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  613. size_t outlen;
  614. int rc;
  615. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  616. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  617. outbuf, sizeof(outbuf), &outlen);
  618. if (rc)
  619. goto fail;
  620. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  621. rc = -EIO;
  622. goto fail;
  623. }
  624. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  625. return 0;
  626. fail:
  627. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  628. __func__, rc);
  629. return rc;
  630. }
  631. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  632. size_t *size_out, size_t *erase_size_out,
  633. bool *protected_out)
  634. {
  635. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  636. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  637. size_t outlen;
  638. int rc;
  639. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  640. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  641. outbuf, sizeof(outbuf), &outlen);
  642. if (rc)
  643. goto fail;
  644. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  645. rc = -EIO;
  646. goto fail;
  647. }
  648. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  649. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  650. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  651. (1 << MC_CMD_NVRAM_PROTECTED_LBN));
  652. return 0;
  653. fail:
  654. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  655. return rc;
  656. }
  657. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  658. {
  659. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  660. int rc;
  661. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  662. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  663. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  664. NULL, 0, NULL);
  665. if (rc)
  666. goto fail;
  667. return 0;
  668. fail:
  669. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  670. return rc;
  671. }
  672. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  673. loff_t offset, u8 *buffer, size_t length)
  674. {
  675. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  676. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  677. size_t outlen;
  678. int rc;
  679. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  680. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  681. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  682. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  683. outbuf, sizeof(outbuf), &outlen);
  684. if (rc)
  685. goto fail;
  686. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  687. return 0;
  688. fail:
  689. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  690. return rc;
  691. }
  692. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  693. loff_t offset, const u8 *buffer, size_t length)
  694. {
  695. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  696. int rc;
  697. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  698. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  699. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  700. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  701. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  702. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  703. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  704. NULL, 0, NULL);
  705. if (rc)
  706. goto fail;
  707. return 0;
  708. fail:
  709. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  710. return rc;
  711. }
  712. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  713. loff_t offset, size_t length)
  714. {
  715. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  716. int rc;
  717. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  718. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  719. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  720. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  721. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  722. NULL, 0, NULL);
  723. if (rc)
  724. goto fail;
  725. return 0;
  726. fail:
  727. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  728. return rc;
  729. }
  730. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  731. {
  732. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  733. int rc;
  734. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  735. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  736. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  737. NULL, 0, NULL);
  738. if (rc)
  739. goto fail;
  740. return 0;
  741. fail:
  742. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  743. return rc;
  744. }
  745. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  746. {
  747. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  748. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  749. int rc;
  750. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  751. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  752. outbuf, sizeof(outbuf), NULL);
  753. if (rc)
  754. return rc;
  755. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  756. case MC_CMD_NVRAM_TEST_PASS:
  757. case MC_CMD_NVRAM_TEST_NOTSUPP:
  758. return 0;
  759. default:
  760. return -EIO;
  761. }
  762. }
  763. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  764. {
  765. u32 nvram_types;
  766. unsigned int type;
  767. int rc;
  768. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  769. if (rc)
  770. goto fail1;
  771. type = 0;
  772. while (nvram_types != 0) {
  773. if (nvram_types & 1) {
  774. rc = efx_mcdi_nvram_test(efx, type);
  775. if (rc)
  776. goto fail2;
  777. }
  778. type++;
  779. nvram_types >>= 1;
  780. }
  781. return 0;
  782. fail2:
  783. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  784. __func__, type);
  785. fail1:
  786. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  787. return rc;
  788. }
  789. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  790. {
  791. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  792. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  793. unsigned int flags, index, ofst;
  794. const char *reason;
  795. size_t outlen;
  796. int retry;
  797. int rc;
  798. /* Attempt to read any stored assertion state before we reboot
  799. * the mcfw out of the assertion handler. Retry twice, once
  800. * because a boot-time assertion might cause this command to fail
  801. * with EINTR. And once again because GET_ASSERTS can race with
  802. * MC_CMD_REBOOT running on the other port. */
  803. retry = 2;
  804. do {
  805. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  806. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  807. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  808. outbuf, sizeof(outbuf), &outlen);
  809. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  810. if (rc)
  811. return rc;
  812. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  813. return -EIO;
  814. /* Print out any recorded assertion state */
  815. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  816. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  817. return 0;
  818. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  819. ? "system-level assertion"
  820. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  821. ? "thread-level assertion"
  822. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  823. ? "watchdog reset"
  824. : "unknown assertion";
  825. netif_err(efx, hw, efx->net_dev,
  826. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  827. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  828. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  829. /* Print out the registers */
  830. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  831. for (index = 1; index < 32; index++) {
  832. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
  833. MCDI_DWORD2(outbuf, ofst));
  834. ofst += sizeof(efx_dword_t);
  835. }
  836. return 0;
  837. }
  838. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  839. {
  840. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  841. /* Atomically reboot the mcfw out of the assertion handler */
  842. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  843. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  844. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  845. efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  846. NULL, 0, NULL);
  847. }
  848. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  849. {
  850. int rc;
  851. rc = efx_mcdi_read_assertion(efx);
  852. if (rc)
  853. return rc;
  854. efx_mcdi_exit_assertion(efx);
  855. return 0;
  856. }
  857. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  858. {
  859. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  860. int rc;
  861. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  862. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  863. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  864. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  865. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  866. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  867. NULL, 0, NULL);
  868. if (rc)
  869. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  870. __func__, rc);
  871. }
  872. int efx_mcdi_reset_port(struct efx_nic *efx)
  873. {
  874. int rc = efx_mcdi_rpc(efx, MC_CMD_PORT_RESET, NULL, 0, NULL, 0, NULL);
  875. if (rc)
  876. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  877. __func__, rc);
  878. return rc;
  879. }
  880. int efx_mcdi_reset_mc(struct efx_nic *efx)
  881. {
  882. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  883. int rc;
  884. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  885. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  886. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  887. NULL, 0, NULL);
  888. /* White is black, and up is down */
  889. if (rc == -EIO)
  890. return 0;
  891. if (rc == 0)
  892. rc = -EIO;
  893. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  894. return rc;
  895. }
  896. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  897. const u8 *mac, int *id_out)
  898. {
  899. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  900. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  901. size_t outlen;
  902. int rc;
  903. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  904. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  905. MC_CMD_FILTER_MODE_SIMPLE);
  906. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  907. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  908. outbuf, sizeof(outbuf), &outlen);
  909. if (rc)
  910. goto fail;
  911. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  912. rc = -EIO;
  913. goto fail;
  914. }
  915. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  916. return 0;
  917. fail:
  918. *id_out = -1;
  919. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  920. return rc;
  921. }
  922. int
  923. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  924. {
  925. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  926. }
  927. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  928. {
  929. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  930. size_t outlen;
  931. int rc;
  932. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  933. outbuf, sizeof(outbuf), &outlen);
  934. if (rc)
  935. goto fail;
  936. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  937. rc = -EIO;
  938. goto fail;
  939. }
  940. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  941. return 0;
  942. fail:
  943. *id_out = -1;
  944. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  945. return rc;
  946. }
  947. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  948. {
  949. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  950. int rc;
  951. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  952. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  953. NULL, 0, NULL);
  954. if (rc)
  955. goto fail;
  956. return 0;
  957. fail:
  958. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  959. return rc;
  960. }
  961. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  962. {
  963. int rc;
  964. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  965. if (rc)
  966. goto fail;
  967. return 0;
  968. fail:
  969. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  970. return rc;
  971. }