intel_crt.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610
  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/i2c.h>
  27. #include <linux/slab.h>
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "drm_crtc.h"
  31. #include "drm_crtc_helper.h"
  32. #include "drm_edid.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. /* Here's the desired hotplug mode */
  37. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  38. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  39. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  40. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  41. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  42. ADPA_CRT_HOTPLUG_ENABLE)
  43. struct intel_crt {
  44. struct intel_encoder base;
  45. bool force_hotplug_required;
  46. };
  47. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  48. {
  49. return container_of(intel_attached_encoder(connector),
  50. struct intel_crt, base);
  51. }
  52. static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
  53. {
  54. struct drm_device *dev = encoder->dev;
  55. struct drm_i915_private *dev_priv = dev->dev_private;
  56. u32 temp, reg;
  57. if (HAS_PCH_SPLIT(dev))
  58. reg = PCH_ADPA;
  59. else
  60. reg = ADPA;
  61. temp = I915_READ(reg);
  62. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  63. temp &= ~ADPA_DAC_ENABLE;
  64. switch(mode) {
  65. case DRM_MODE_DPMS_ON:
  66. temp |= ADPA_DAC_ENABLE;
  67. break;
  68. case DRM_MODE_DPMS_STANDBY:
  69. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  70. break;
  71. case DRM_MODE_DPMS_SUSPEND:
  72. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  73. break;
  74. case DRM_MODE_DPMS_OFF:
  75. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  76. break;
  77. }
  78. I915_WRITE(reg, temp);
  79. }
  80. static int intel_crt_mode_valid(struct drm_connector *connector,
  81. struct drm_display_mode *mode)
  82. {
  83. struct drm_device *dev = connector->dev;
  84. int max_clock = 0;
  85. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  86. return MODE_NO_DBLESCAN;
  87. if (mode->clock < 25000)
  88. return MODE_CLOCK_LOW;
  89. if (IS_GEN2(dev))
  90. max_clock = 350000;
  91. else
  92. max_clock = 400000;
  93. if (mode->clock > max_clock)
  94. return MODE_CLOCK_HIGH;
  95. return MODE_OK;
  96. }
  97. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  98. struct drm_display_mode *mode,
  99. struct drm_display_mode *adjusted_mode)
  100. {
  101. return true;
  102. }
  103. static void intel_crt_mode_set(struct drm_encoder *encoder,
  104. struct drm_display_mode *mode,
  105. struct drm_display_mode *adjusted_mode)
  106. {
  107. struct drm_device *dev = encoder->dev;
  108. struct drm_crtc *crtc = encoder->crtc;
  109. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  110. struct drm_i915_private *dev_priv = dev->dev_private;
  111. int dpll_md_reg;
  112. u32 adpa, dpll_md;
  113. u32 adpa_reg;
  114. dpll_md_reg = DPLL_MD(intel_crtc->pipe);
  115. if (HAS_PCH_SPLIT(dev))
  116. adpa_reg = PCH_ADPA;
  117. else
  118. adpa_reg = ADPA;
  119. /*
  120. * Disable separate mode multiplier used when cloning SDVO to CRT
  121. * XXX this needs to be adjusted when we really are cloning
  122. */
  123. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  124. dpll_md = I915_READ(dpll_md_reg);
  125. I915_WRITE(dpll_md_reg,
  126. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  127. }
  128. adpa = ADPA_HOTPLUG_BITS;
  129. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  130. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  131. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  132. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  133. if (intel_crtc->pipe == 0) {
  134. if (HAS_PCH_CPT(dev))
  135. adpa |= PORT_TRANS_A_SEL_CPT;
  136. else
  137. adpa |= ADPA_PIPE_A_SELECT;
  138. } else {
  139. if (HAS_PCH_CPT(dev))
  140. adpa |= PORT_TRANS_B_SEL_CPT;
  141. else
  142. adpa |= ADPA_PIPE_B_SELECT;
  143. }
  144. if (!HAS_PCH_SPLIT(dev))
  145. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  146. I915_WRITE(adpa_reg, adpa);
  147. }
  148. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  149. {
  150. struct drm_device *dev = connector->dev;
  151. struct intel_crt *crt = intel_attached_crt(connector);
  152. struct drm_i915_private *dev_priv = dev->dev_private;
  153. u32 adpa;
  154. bool ret;
  155. /* The first time through, trigger an explicit detection cycle */
  156. if (crt->force_hotplug_required) {
  157. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  158. u32 save_adpa;
  159. crt->force_hotplug_required = 0;
  160. save_adpa = adpa = I915_READ(PCH_ADPA);
  161. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  162. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  163. if (turn_off_dac)
  164. adpa &= ~ADPA_DAC_ENABLE;
  165. I915_WRITE(PCH_ADPA, adpa);
  166. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  167. 1000))
  168. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  169. if (turn_off_dac) {
  170. I915_WRITE(PCH_ADPA, save_adpa);
  171. POSTING_READ(PCH_ADPA);
  172. }
  173. }
  174. /* Check the status to see if both blue and green are on now */
  175. adpa = I915_READ(PCH_ADPA);
  176. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  177. ret = true;
  178. else
  179. ret = false;
  180. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  181. return ret;
  182. }
  183. /**
  184. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  185. *
  186. * Not for i915G/i915GM
  187. *
  188. * \return true if CRT is connected.
  189. * \return false if CRT is disconnected.
  190. */
  191. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  192. {
  193. struct drm_device *dev = connector->dev;
  194. struct drm_i915_private *dev_priv = dev->dev_private;
  195. u32 hotplug_en, orig, stat;
  196. bool ret = false;
  197. int i, tries = 0;
  198. if (HAS_PCH_SPLIT(dev))
  199. return intel_ironlake_crt_detect_hotplug(connector);
  200. /*
  201. * On 4 series desktop, CRT detect sequence need to be done twice
  202. * to get a reliable result.
  203. */
  204. if (IS_G4X(dev) && !IS_GM45(dev))
  205. tries = 2;
  206. else
  207. tries = 1;
  208. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  209. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  210. for (i = 0; i < tries ; i++) {
  211. /* turn on the FORCE_DETECT */
  212. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  213. /* wait for FORCE_DETECT to go off */
  214. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  215. CRT_HOTPLUG_FORCE_DETECT) == 0,
  216. 1000))
  217. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  218. }
  219. stat = I915_READ(PORT_HOTPLUG_STAT);
  220. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  221. ret = true;
  222. /* clear the interrupt we just generated, if any */
  223. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  224. /* and put the bits back */
  225. I915_WRITE(PORT_HOTPLUG_EN, orig);
  226. return ret;
  227. }
  228. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  229. {
  230. struct intel_crt *crt = intel_attached_crt(connector);
  231. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  232. /* CRT should always be at 0, but check anyway */
  233. if (crt->base.type != INTEL_OUTPUT_ANALOG)
  234. return false;
  235. if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
  236. struct edid *edid;
  237. bool is_digital = false;
  238. edid = drm_get_edid(connector,
  239. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  240. /*
  241. * This may be a DVI-I connector with a shared DDC
  242. * link between analog and digital outputs, so we
  243. * have to check the EDID input spec of the attached device.
  244. *
  245. * On the other hand, what should we do if it is a broken EDID?
  246. */
  247. if (edid != NULL) {
  248. is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  249. connector->display_info.raw_edid = NULL;
  250. kfree(edid);
  251. }
  252. if (!is_digital) {
  253. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  254. return true;
  255. } else {
  256. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  257. }
  258. }
  259. return false;
  260. }
  261. static enum drm_connector_status
  262. intel_crt_load_detect(struct intel_crt *crt)
  263. {
  264. struct drm_device *dev = crt->base.base.dev;
  265. struct drm_i915_private *dev_priv = dev->dev_private;
  266. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  267. uint32_t save_bclrpat;
  268. uint32_t save_vtotal;
  269. uint32_t vtotal, vactive;
  270. uint32_t vsample;
  271. uint32_t vblank, vblank_start, vblank_end;
  272. uint32_t dsl;
  273. uint32_t bclrpat_reg;
  274. uint32_t vtotal_reg;
  275. uint32_t vblank_reg;
  276. uint32_t vsync_reg;
  277. uint32_t pipeconf_reg;
  278. uint32_t pipe_dsl_reg;
  279. uint8_t st00;
  280. enum drm_connector_status status;
  281. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  282. bclrpat_reg = BCLRPAT(pipe);
  283. vtotal_reg = VTOTAL(pipe);
  284. vblank_reg = VBLANK(pipe);
  285. vsync_reg = VSYNC(pipe);
  286. pipeconf_reg = PIPECONF(pipe);
  287. pipe_dsl_reg = PIPEDSL(pipe);
  288. save_bclrpat = I915_READ(bclrpat_reg);
  289. save_vtotal = I915_READ(vtotal_reg);
  290. vblank = I915_READ(vblank_reg);
  291. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  292. vactive = (save_vtotal & 0x7ff) + 1;
  293. vblank_start = (vblank & 0xfff) + 1;
  294. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  295. /* Set the border color to purple. */
  296. I915_WRITE(bclrpat_reg, 0x500050);
  297. if (!IS_GEN2(dev)) {
  298. uint32_t pipeconf = I915_READ(pipeconf_reg);
  299. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  300. POSTING_READ(pipeconf_reg);
  301. /* Wait for next Vblank to substitue
  302. * border color for Color info */
  303. intel_wait_for_vblank(dev, pipe);
  304. st00 = I915_READ8(VGA_MSR_WRITE);
  305. status = ((st00 & (1 << 4)) != 0) ?
  306. connector_status_connected :
  307. connector_status_disconnected;
  308. I915_WRITE(pipeconf_reg, pipeconf);
  309. } else {
  310. bool restore_vblank = false;
  311. int count, detect;
  312. /*
  313. * If there isn't any border, add some.
  314. * Yes, this will flicker
  315. */
  316. if (vblank_start <= vactive && vblank_end >= vtotal) {
  317. uint32_t vsync = I915_READ(vsync_reg);
  318. uint32_t vsync_start = (vsync & 0xffff) + 1;
  319. vblank_start = vsync_start;
  320. I915_WRITE(vblank_reg,
  321. (vblank_start - 1) |
  322. ((vblank_end - 1) << 16));
  323. restore_vblank = true;
  324. }
  325. /* sample in the vertical border, selecting the larger one */
  326. if (vblank_start - vactive >= vtotal - vblank_end)
  327. vsample = (vblank_start + vactive) >> 1;
  328. else
  329. vsample = (vtotal + vblank_end) >> 1;
  330. /*
  331. * Wait for the border to be displayed
  332. */
  333. while (I915_READ(pipe_dsl_reg) >= vactive)
  334. ;
  335. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  336. ;
  337. /*
  338. * Watch ST00 for an entire scanline
  339. */
  340. detect = 0;
  341. count = 0;
  342. do {
  343. count++;
  344. /* Read the ST00 VGA status register */
  345. st00 = I915_READ8(VGA_MSR_WRITE);
  346. if (st00 & (1 << 4))
  347. detect++;
  348. } while ((I915_READ(pipe_dsl_reg) == dsl));
  349. /* restore vblank if necessary */
  350. if (restore_vblank)
  351. I915_WRITE(vblank_reg, vblank);
  352. /*
  353. * If more than 3/4 of the scanline detected a monitor,
  354. * then it is assumed to be present. This works even on i830,
  355. * where there isn't any way to force the border color across
  356. * the screen
  357. */
  358. status = detect * 4 > count * 3 ?
  359. connector_status_connected :
  360. connector_status_disconnected;
  361. }
  362. /* Restore previous settings */
  363. I915_WRITE(bclrpat_reg, save_bclrpat);
  364. return status;
  365. }
  366. static enum drm_connector_status
  367. intel_crt_detect(struct drm_connector *connector, bool force)
  368. {
  369. struct drm_device *dev = connector->dev;
  370. struct intel_crt *crt = intel_attached_crt(connector);
  371. struct drm_crtc *crtc;
  372. enum drm_connector_status status;
  373. if (I915_HAS_HOTPLUG(dev)) {
  374. if (intel_crt_detect_hotplug(connector)) {
  375. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  376. return connector_status_connected;
  377. } else {
  378. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  379. return connector_status_disconnected;
  380. }
  381. }
  382. if (intel_crt_detect_ddc(connector))
  383. return connector_status_connected;
  384. if (!force)
  385. return connector->status;
  386. /* for pre-945g platforms use load detect */
  387. crtc = crt->base.base.crtc;
  388. if (crtc && crtc->enabled) {
  389. status = intel_crt_load_detect(crt);
  390. } else {
  391. struct intel_load_detect_pipe tmp;
  392. if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
  393. &tmp)) {
  394. if (intel_crt_detect_ddc(connector))
  395. status = connector_status_connected;
  396. else
  397. status = intel_crt_load_detect(crt);
  398. intel_release_load_detect_pipe(&crt->base, connector,
  399. &tmp);
  400. } else
  401. status = connector_status_unknown;
  402. }
  403. return status;
  404. }
  405. static void intel_crt_destroy(struct drm_connector *connector)
  406. {
  407. drm_sysfs_connector_remove(connector);
  408. drm_connector_cleanup(connector);
  409. kfree(connector);
  410. }
  411. static int intel_crt_get_modes(struct drm_connector *connector)
  412. {
  413. struct drm_device *dev = connector->dev;
  414. struct drm_i915_private *dev_priv = dev->dev_private;
  415. int ret;
  416. ret = intel_ddc_get_modes(connector,
  417. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  418. if (ret || !IS_G4X(dev))
  419. return ret;
  420. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  421. return intel_ddc_get_modes(connector,
  422. &dev_priv->gmbus[GMBUS_PORT_DPB].adapter);
  423. }
  424. static int intel_crt_set_property(struct drm_connector *connector,
  425. struct drm_property *property,
  426. uint64_t value)
  427. {
  428. return 0;
  429. }
  430. static void intel_crt_reset(struct drm_connector *connector)
  431. {
  432. struct drm_device *dev = connector->dev;
  433. struct intel_crt *crt = intel_attached_crt(connector);
  434. if (HAS_PCH_SPLIT(dev))
  435. crt->force_hotplug_required = 1;
  436. }
  437. /*
  438. * Routines for controlling stuff on the analog port
  439. */
  440. static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
  441. .dpms = intel_crt_dpms,
  442. .mode_fixup = intel_crt_mode_fixup,
  443. .prepare = intel_encoder_prepare,
  444. .commit = intel_encoder_commit,
  445. .mode_set = intel_crt_mode_set,
  446. };
  447. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  448. .reset = intel_crt_reset,
  449. .dpms = drm_helper_connector_dpms,
  450. .detect = intel_crt_detect,
  451. .fill_modes = drm_helper_probe_single_connector_modes,
  452. .destroy = intel_crt_destroy,
  453. .set_property = intel_crt_set_property,
  454. };
  455. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  456. .mode_valid = intel_crt_mode_valid,
  457. .get_modes = intel_crt_get_modes,
  458. .best_encoder = intel_best_encoder,
  459. };
  460. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  461. .destroy = intel_encoder_destroy,
  462. };
  463. void intel_crt_init(struct drm_device *dev)
  464. {
  465. struct drm_connector *connector;
  466. struct intel_crt *crt;
  467. struct intel_connector *intel_connector;
  468. struct drm_i915_private *dev_priv = dev->dev_private;
  469. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  470. if (!crt)
  471. return;
  472. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  473. if (!intel_connector) {
  474. kfree(crt);
  475. return;
  476. }
  477. connector = &intel_connector->base;
  478. drm_connector_init(dev, &intel_connector->base,
  479. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  480. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  481. DRM_MODE_ENCODER_DAC);
  482. intel_connector_attach_encoder(intel_connector, &crt->base);
  483. crt->base.type = INTEL_OUTPUT_ANALOG;
  484. crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT |
  485. 1 << INTEL_ANALOG_CLONE_BIT |
  486. 1 << INTEL_SDVO_LVDS_CLONE_BIT);
  487. crt->base.crtc_mask = (1 << 0) | (1 << 1);
  488. connector->interlace_allowed = 1;
  489. connector->doublescan_allowed = 0;
  490. drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
  491. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  492. drm_sysfs_connector_add(connector);
  493. if (I915_HAS_HOTPLUG(dev))
  494. connector->polled = DRM_CONNECTOR_POLL_HPD;
  495. else
  496. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  497. /*
  498. * Configure the automatic hotplug detection stuff
  499. */
  500. crt->force_hotplug_required = 0;
  501. if (HAS_PCH_SPLIT(dev)) {
  502. u32 adpa;
  503. adpa = I915_READ(PCH_ADPA);
  504. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  505. adpa |= ADPA_HOTPLUG_BITS;
  506. I915_WRITE(PCH_ADPA, adpa);
  507. POSTING_READ(PCH_ADPA);
  508. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  509. crt->force_hotplug_required = 1;
  510. }
  511. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  512. }