pata_cs5520.c 8.2 KB

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  1. /*
  2. * IDE tuning and bus mastering support for the CS5510/CS5520
  3. * chipsets
  4. *
  5. * The CS5510/CS5520 are slightly unusual devices. Unlike the
  6. * typical IDE controllers they do bus mastering with the drive in
  7. * PIO mode and smarter silicon.
  8. *
  9. * The practical upshot of this is that we must always tune the
  10. * drive for the right PIO mode. We must also ignore all the blacklists
  11. * and the drive bus mastering DMA information. Also to confuse matters
  12. * further we can do DMA on PIO only drives.
  13. *
  14. * DMA on the 5510 also requires we disable_hlt() during DMA on early
  15. * revisions.
  16. *
  17. * *** This driver is strictly experimental ***
  18. *
  19. * (c) Copyright Red Hat Inc 2002
  20. *
  21. * This program is free software; you can redistribute it and/or modify it
  22. * under the terms of the GNU General Public License as published by the
  23. * Free Software Foundation; either version 2, or (at your option) any
  24. * later version.
  25. *
  26. * This program is distributed in the hope that it will be useful, but
  27. * WITHOUT ANY WARRANTY; without even the implied warranty of
  28. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  29. * General Public License for more details.
  30. *
  31. * Documentation:
  32. * Not publicly available.
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/module.h>
  36. #include <linux/pci.h>
  37. #include <linux/init.h>
  38. #include <linux/blkdev.h>
  39. #include <linux/delay.h>
  40. #include <scsi/scsi_host.h>
  41. #include <linux/libata.h>
  42. #define DRV_NAME "pata_cs5520"
  43. #define DRV_VERSION "0.6.6"
  44. struct pio_clocks
  45. {
  46. int address;
  47. int assert;
  48. int recovery;
  49. };
  50. static const struct pio_clocks cs5520_pio_clocks[]={
  51. {3, 6, 11},
  52. {2, 5, 6},
  53. {1, 4, 3},
  54. {1, 3, 2},
  55. {1, 2, 1}
  56. };
  57. /**
  58. * cs5520_set_timings - program PIO timings
  59. * @ap: ATA port
  60. * @adev: ATA device
  61. *
  62. * Program the PIO mode timings for the controller according to the pio
  63. * clocking table.
  64. */
  65. static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
  66. {
  67. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  68. int slave = adev->devno;
  69. pio -= XFER_PIO_0;
  70. /* Channel command timing */
  71. pci_write_config_byte(pdev, 0x62 + ap->port_no,
  72. (cs5520_pio_clocks[pio].recovery << 4) |
  73. (cs5520_pio_clocks[pio].assert));
  74. /* FIXME: should these use address ? */
  75. /* Read command timing */
  76. pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave,
  77. (cs5520_pio_clocks[pio].recovery << 4) |
  78. (cs5520_pio_clocks[pio].assert));
  79. /* Write command timing */
  80. pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave,
  81. (cs5520_pio_clocks[pio].recovery << 4) |
  82. (cs5520_pio_clocks[pio].assert));
  83. }
  84. /**
  85. * cs5520_set_piomode - program PIO timings
  86. * @ap: ATA port
  87. * @adev: ATA device
  88. *
  89. * Program the PIO mode timings for the controller according to the pio
  90. * clocking table.
  91. */
  92. static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
  93. {
  94. cs5520_set_timings(ap, adev, adev->pio_mode);
  95. }
  96. static struct scsi_host_template cs5520_sht = {
  97. ATA_BMDMA_SHT(DRV_NAME),
  98. .sg_tablesize = LIBATA_DUMB_MAX_PRD,
  99. };
  100. static struct ata_port_operations cs5520_port_ops = {
  101. .inherits = &ata_bmdma_port_ops,
  102. .qc_prep = ata_bmdma_dumb_qc_prep,
  103. .cable_detect = ata_cable_40wire,
  104. .set_piomode = cs5520_set_piomode,
  105. };
  106. static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  107. {
  108. static const unsigned int cmd_port[] = { 0x1F0, 0x170 };
  109. static const unsigned int ctl_port[] = { 0x3F6, 0x376 };
  110. struct ata_port_info pi = {
  111. .flags = ATA_FLAG_SLAVE_POSS,
  112. .pio_mask = ATA_PIO4,
  113. .port_ops = &cs5520_port_ops,
  114. };
  115. const struct ata_port_info *ppi[2];
  116. u8 pcicfg;
  117. void __iomem *iomap[5];
  118. struct ata_host *host;
  119. struct ata_ioports *ioaddr;
  120. int i, rc;
  121. rc = pcim_enable_device(pdev);
  122. if (rc)
  123. return rc;
  124. /* IDE port enable bits */
  125. pci_read_config_byte(pdev, 0x60, &pcicfg);
  126. /* Check if the ATA ports are enabled */
  127. if ((pcicfg & 3) == 0)
  128. return -ENODEV;
  129. ppi[0] = ppi[1] = &ata_dummy_port_info;
  130. if (pcicfg & 1)
  131. ppi[0] = &pi;
  132. if (pcicfg & 2)
  133. ppi[1] = &pi;
  134. if ((pcicfg & 0x40) == 0) {
  135. dev_printk(KERN_WARNING, &pdev->dev,
  136. "DMA mode disabled. Enabling.\n");
  137. pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
  138. }
  139. pi.mwdma_mask = id->driver_data;
  140. host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
  141. if (!host)
  142. return -ENOMEM;
  143. /* Perform set up for DMA */
  144. if (pci_enable_device_io(pdev)) {
  145. printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
  146. return -ENODEV;
  147. }
  148. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  149. printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
  150. return -ENODEV;
  151. }
  152. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  153. printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
  154. return -ENODEV;
  155. }
  156. /* Map IO ports and initialize host accordingly */
  157. iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8);
  158. iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1);
  159. iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8);
  160. iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1);
  161. iomap[4] = pcim_iomap(pdev, 2, 0);
  162. if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4])
  163. return -ENOMEM;
  164. ioaddr = &host->ports[0]->ioaddr;
  165. ioaddr->cmd_addr = iomap[0];
  166. ioaddr->ctl_addr = iomap[1];
  167. ioaddr->altstatus_addr = iomap[1];
  168. ioaddr->bmdma_addr = iomap[4];
  169. ata_sff_std_ports(ioaddr);
  170. ata_port_desc(host->ports[0],
  171. "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]);
  172. ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma");
  173. ioaddr = &host->ports[1]->ioaddr;
  174. ioaddr->cmd_addr = iomap[2];
  175. ioaddr->ctl_addr = iomap[3];
  176. ioaddr->altstatus_addr = iomap[3];
  177. ioaddr->bmdma_addr = iomap[4] + 8;
  178. ata_sff_std_ports(ioaddr);
  179. ata_port_desc(host->ports[1],
  180. "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]);
  181. ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma");
  182. /* activate the host */
  183. pci_set_master(pdev);
  184. rc = ata_host_start(host);
  185. if (rc)
  186. return rc;
  187. for (i = 0; i < 2; i++) {
  188. static const int irq[] = { 14, 15 };
  189. struct ata_port *ap = host->ports[i];
  190. if (ata_port_is_dummy(ap))
  191. continue;
  192. rc = devm_request_irq(&pdev->dev, irq[ap->port_no],
  193. ata_bmdma_interrupt, 0, DRV_NAME, host);
  194. if (rc)
  195. return rc;
  196. ata_port_desc(ap, "irq %d", irq[i]);
  197. }
  198. return ata_host_register(host, &cs5520_sht);
  199. }
  200. #ifdef CONFIG_PM
  201. /**
  202. * cs5520_reinit_one - device resume
  203. * @pdev: PCI device
  204. *
  205. * Do any reconfiguration work needed by a resume from RAM. We need
  206. * to restore DMA mode support on BIOSen which disabled it
  207. */
  208. static int cs5520_reinit_one(struct pci_dev *pdev)
  209. {
  210. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  211. u8 pcicfg;
  212. int rc;
  213. rc = ata_pci_device_do_resume(pdev);
  214. if (rc)
  215. return rc;
  216. pci_read_config_byte(pdev, 0x60, &pcicfg);
  217. if ((pcicfg & 0x40) == 0)
  218. pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
  219. ata_host_resume(host);
  220. return 0;
  221. }
  222. /**
  223. * cs5520_pci_device_suspend - device suspend
  224. * @pdev: PCI device
  225. *
  226. * We have to cut and waste bits from the standard method because
  227. * the 5520 is a bit odd and not just a pure ATA device. As a result
  228. * we must not disable it. The needed code is short and this avoids
  229. * chip specific mess in the core code.
  230. */
  231. static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
  232. {
  233. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  234. int rc = 0;
  235. rc = ata_host_suspend(host, mesg);
  236. if (rc)
  237. return rc;
  238. pci_save_state(pdev);
  239. return 0;
  240. }
  241. #endif /* CONFIG_PM */
  242. /* For now keep DMA off. We can set it for all but A rev CS5510 once the
  243. core ATA code can handle it */
  244. static const struct pci_device_id pata_cs5520[] = {
  245. { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
  246. { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
  247. { },
  248. };
  249. static struct pci_driver cs5520_pci_driver = {
  250. .name = DRV_NAME,
  251. .id_table = pata_cs5520,
  252. .probe = cs5520_init_one,
  253. .remove = ata_pci_remove_one,
  254. #ifdef CONFIG_PM
  255. .suspend = cs5520_pci_device_suspend,
  256. .resume = cs5520_reinit_one,
  257. #endif
  258. };
  259. static int __init cs5520_init(void)
  260. {
  261. return pci_register_driver(&cs5520_pci_driver);
  262. }
  263. static void __exit cs5520_exit(void)
  264. {
  265. pci_unregister_driver(&cs5520_pci_driver);
  266. }
  267. MODULE_AUTHOR("Alan Cox");
  268. MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
  269. MODULE_LICENSE("GPL");
  270. MODULE_DEVICE_TABLE(pci, pata_cs5520);
  271. MODULE_VERSION(DRV_VERSION);
  272. module_init(cs5520_init);
  273. module_exit(cs5520_exit);