direct.c 6.4 KB

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  1. /*
  2. * direct.c - Low-level direct PCI config space access
  3. */
  4. #include <linux/pci.h>
  5. #include <linux/init.h>
  6. #include <linux/dmi.h>
  7. #include <asm/pci_x86.h>
  8. /*
  9. * Functions for accessing PCI base (first 256 bytes) and extended
  10. * (4096 bytes per PCI function) configuration space with type 1
  11. * accesses.
  12. */
  13. #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
  14. (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
  15. | (devfn << 8) | (reg & 0xFC))
  16. static int pci_conf1_read(unsigned int seg, unsigned int bus,
  17. unsigned int devfn, int reg, int len, u32 *value)
  18. {
  19. unsigned long flags;
  20. if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
  21. *value = -1;
  22. return -EINVAL;
  23. }
  24. raw_spin_lock_irqsave(&pci_config_lock, flags);
  25. outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
  26. switch (len) {
  27. case 1:
  28. *value = inb(0xCFC + (reg & 3));
  29. break;
  30. case 2:
  31. *value = inw(0xCFC + (reg & 2));
  32. break;
  33. case 4:
  34. *value = inl(0xCFC);
  35. break;
  36. }
  37. raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  38. return 0;
  39. }
  40. static int pci_conf1_write(unsigned int seg, unsigned int bus,
  41. unsigned int devfn, int reg, int len, u32 value)
  42. {
  43. unsigned long flags;
  44. if ((bus > 255) || (devfn > 255) || (reg > 4095))
  45. return -EINVAL;
  46. raw_spin_lock_irqsave(&pci_config_lock, flags);
  47. outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
  48. switch (len) {
  49. case 1:
  50. outb((u8)value, 0xCFC + (reg & 3));
  51. break;
  52. case 2:
  53. outw((u16)value, 0xCFC + (reg & 2));
  54. break;
  55. case 4:
  56. outl((u32)value, 0xCFC);
  57. break;
  58. }
  59. raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  60. return 0;
  61. }
  62. #undef PCI_CONF1_ADDRESS
  63. struct pci_raw_ops pci_direct_conf1 = {
  64. .read = pci_conf1_read,
  65. .write = pci_conf1_write,
  66. };
  67. /*
  68. * Functions for accessing PCI configuration space with type 2 accesses
  69. */
  70. #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
  71. static int pci_conf2_read(unsigned int seg, unsigned int bus,
  72. unsigned int devfn, int reg, int len, u32 *value)
  73. {
  74. unsigned long flags;
  75. int dev, fn;
  76. if ((bus > 255) || (devfn > 255) || (reg > 255)) {
  77. *value = -1;
  78. return -EINVAL;
  79. }
  80. dev = PCI_SLOT(devfn);
  81. fn = PCI_FUNC(devfn);
  82. if (dev & 0x10)
  83. return PCIBIOS_DEVICE_NOT_FOUND;
  84. raw_spin_lock_irqsave(&pci_config_lock, flags);
  85. outb((u8)(0xF0 | (fn << 1)), 0xCF8);
  86. outb((u8)bus, 0xCFA);
  87. switch (len) {
  88. case 1:
  89. *value = inb(PCI_CONF2_ADDRESS(dev, reg));
  90. break;
  91. case 2:
  92. *value = inw(PCI_CONF2_ADDRESS(dev, reg));
  93. break;
  94. case 4:
  95. *value = inl(PCI_CONF2_ADDRESS(dev, reg));
  96. break;
  97. }
  98. outb(0, 0xCF8);
  99. raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  100. return 0;
  101. }
  102. static int pci_conf2_write(unsigned int seg, unsigned int bus,
  103. unsigned int devfn, int reg, int len, u32 value)
  104. {
  105. unsigned long flags;
  106. int dev, fn;
  107. if ((bus > 255) || (devfn > 255) || (reg > 255))
  108. return -EINVAL;
  109. dev = PCI_SLOT(devfn);
  110. fn = PCI_FUNC(devfn);
  111. if (dev & 0x10)
  112. return PCIBIOS_DEVICE_NOT_FOUND;
  113. raw_spin_lock_irqsave(&pci_config_lock, flags);
  114. outb((u8)(0xF0 | (fn << 1)), 0xCF8);
  115. outb((u8)bus, 0xCFA);
  116. switch (len) {
  117. case 1:
  118. outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
  119. break;
  120. case 2:
  121. outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
  122. break;
  123. case 4:
  124. outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
  125. break;
  126. }
  127. outb(0, 0xCF8);
  128. raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  129. return 0;
  130. }
  131. #undef PCI_CONF2_ADDRESS
  132. struct pci_raw_ops pci_direct_conf2 = {
  133. .read = pci_conf2_read,
  134. .write = pci_conf2_write,
  135. };
  136. /*
  137. * Before we decide to use direct hardware access mechanisms, we try to do some
  138. * trivial checks to ensure it at least _seems_ to be working -- we just test
  139. * whether bus 00 contains a host bridge (this is similar to checking
  140. * techniques used in XFree86, but ours should be more reliable since we
  141. * attempt to make use of direct access hints provided by the PCI BIOS).
  142. *
  143. * This should be close to trivial, but it isn't, because there are buggy
  144. * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
  145. */
  146. static int __init pci_sanity_check(struct pci_raw_ops *o)
  147. {
  148. u32 x = 0;
  149. int year, devfn;
  150. if (pci_probe & PCI_NO_CHECKS)
  151. return 1;
  152. /* Assume Type 1 works for newer systems.
  153. This handles machines that don't have anything on PCI Bus 0. */
  154. dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL);
  155. if (year >= 2001)
  156. return 1;
  157. for (devfn = 0; devfn < 0x100; devfn++) {
  158. if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
  159. continue;
  160. if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)
  161. return 1;
  162. if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
  163. continue;
  164. if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)
  165. return 1;
  166. }
  167. DBG(KERN_WARNING "PCI: Sanity check failed\n");
  168. return 0;
  169. }
  170. static int __init pci_check_type1(void)
  171. {
  172. unsigned long flags;
  173. unsigned int tmp;
  174. int works = 0;
  175. local_irq_save(flags);
  176. outb(0x01, 0xCFB);
  177. tmp = inl(0xCF8);
  178. outl(0x80000000, 0xCF8);
  179. if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) {
  180. works = 1;
  181. }
  182. outl(tmp, 0xCF8);
  183. local_irq_restore(flags);
  184. return works;
  185. }
  186. static int __init pci_check_type2(void)
  187. {
  188. unsigned long flags;
  189. int works = 0;
  190. local_irq_save(flags);
  191. outb(0x00, 0xCFB);
  192. outb(0x00, 0xCF8);
  193. outb(0x00, 0xCFA);
  194. if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 &&
  195. pci_sanity_check(&pci_direct_conf2)) {
  196. works = 1;
  197. }
  198. local_irq_restore(flags);
  199. return works;
  200. }
  201. void __init pci_direct_init(int type)
  202. {
  203. if (type == 0)
  204. return;
  205. printk(KERN_INFO "PCI: Using configuration type %d for base access\n",
  206. type);
  207. if (type == 1) {
  208. raw_pci_ops = &pci_direct_conf1;
  209. if (raw_pci_ext_ops)
  210. return;
  211. if (!(pci_probe & PCI_HAS_IO_ECS))
  212. return;
  213. printk(KERN_INFO "PCI: Using configuration type 1 "
  214. "for extended access\n");
  215. raw_pci_ext_ops = &pci_direct_conf1;
  216. return;
  217. }
  218. raw_pci_ops = &pci_direct_conf2;
  219. }
  220. int __init pci_direct_probe(void)
  221. {
  222. if ((pci_probe & PCI_PROBE_CONF1) == 0)
  223. goto type2;
  224. if (!request_region(0xCF8, 8, "PCI conf1"))
  225. goto type2;
  226. if (pci_check_type1()) {
  227. raw_pci_ops = &pci_direct_conf1;
  228. port_cf9_safe = true;
  229. return 1;
  230. }
  231. release_region(0xCF8, 8);
  232. type2:
  233. if ((pci_probe & PCI_PROBE_CONF2) == 0)
  234. return 0;
  235. if (!request_region(0xCF8, 4, "PCI conf2"))
  236. return 0;
  237. if (!request_region(0xC000, 0x1000, "PCI conf2"))
  238. goto fail2;
  239. if (pci_check_type2()) {
  240. raw_pci_ops = &pci_direct_conf2;
  241. port_cf9_safe = true;
  242. return 2;
  243. }
  244. release_region(0xC000, 0x1000);
  245. fail2:
  246. release_region(0xCF8, 4);
  247. return 0;
  248. }