devicetree.c 8.9 KB

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  1. /*
  2. * Architecture specific OF callbacks.
  3. */
  4. #include <linux/bootmem.h>
  5. #include <linux/io.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/list.h>
  8. #include <linux/of.h>
  9. #include <linux/of_fdt.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/slab.h>
  14. #include <linux/pci.h>
  15. #include <linux/of_pci.h>
  16. #include <linux/initrd.h>
  17. #include <asm/hpet.h>
  18. #include <asm/irq_controller.h>
  19. #include <asm/apic.h>
  20. #include <asm/pci_x86.h>
  21. __initdata u64 initial_dtb;
  22. char __initdata cmd_line[COMMAND_LINE_SIZE];
  23. static LIST_HEAD(irq_domains);
  24. static DEFINE_RAW_SPINLOCK(big_irq_lock);
  25. int __initdata of_ioapic;
  26. #ifdef CONFIG_X86_IO_APIC
  27. static void add_interrupt_host(struct irq_domain *ih)
  28. {
  29. unsigned long flags;
  30. raw_spin_lock_irqsave(&big_irq_lock, flags);
  31. list_add(&ih->l, &irq_domains);
  32. raw_spin_unlock_irqrestore(&big_irq_lock, flags);
  33. }
  34. #endif
  35. static struct irq_domain *get_ih_from_node(struct device_node *controller)
  36. {
  37. struct irq_domain *ih, *found = NULL;
  38. unsigned long flags;
  39. raw_spin_lock_irqsave(&big_irq_lock, flags);
  40. list_for_each_entry(ih, &irq_domains, l) {
  41. if (ih->controller == controller) {
  42. found = ih;
  43. break;
  44. }
  45. }
  46. raw_spin_unlock_irqrestore(&big_irq_lock, flags);
  47. return found;
  48. }
  49. unsigned int irq_create_of_mapping(struct device_node *controller,
  50. const u32 *intspec, unsigned int intsize)
  51. {
  52. struct irq_domain *ih;
  53. u32 virq, type;
  54. int ret;
  55. ih = get_ih_from_node(controller);
  56. if (!ih)
  57. return 0;
  58. ret = ih->xlate(ih, intspec, intsize, &virq, &type);
  59. if (ret)
  60. return 0;
  61. if (type == IRQ_TYPE_NONE)
  62. return virq;
  63. irq_set_irq_type(virq, type);
  64. return virq;
  65. }
  66. EXPORT_SYMBOL_GPL(irq_create_of_mapping);
  67. unsigned long pci_address_to_pio(phys_addr_t address)
  68. {
  69. /*
  70. * The ioport address can be directly used by inX / outX
  71. */
  72. BUG_ON(address >= (1 << 16));
  73. return (unsigned long)address;
  74. }
  75. EXPORT_SYMBOL_GPL(pci_address_to_pio);
  76. void __init early_init_dt_scan_chosen_arch(unsigned long node)
  77. {
  78. BUG();
  79. }
  80. void __init early_init_dt_add_memory_arch(u64 base, u64 size)
  81. {
  82. BUG();
  83. }
  84. void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
  85. {
  86. return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
  87. }
  88. #ifdef CONFIG_BLK_DEV_INITRD
  89. void __init early_init_dt_setup_initrd_arch(unsigned long start,
  90. unsigned long end)
  91. {
  92. initrd_start = (unsigned long)__va(start);
  93. initrd_end = (unsigned long)__va(end);
  94. initrd_below_start_ok = 1;
  95. }
  96. #endif
  97. void __init add_dtb(u64 data)
  98. {
  99. initial_dtb = data + offsetof(struct setup_data, data);
  100. }
  101. /*
  102. * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
  103. */
  104. static struct of_device_id __initdata ce4100_ids[] = {
  105. { .compatible = "intel,ce4100-cp", },
  106. { .compatible = "isa", },
  107. { .compatible = "pci", },
  108. {},
  109. };
  110. static int __init add_bus_probe(void)
  111. {
  112. if (!of_have_populated_dt())
  113. return 0;
  114. return of_platform_bus_probe(NULL, ce4100_ids, NULL);
  115. }
  116. module_init(add_bus_probe);
  117. #ifdef CONFIG_PCI
  118. static int x86_of_pci_irq_enable(struct pci_dev *dev)
  119. {
  120. struct of_irq oirq;
  121. u32 virq;
  122. int ret;
  123. u8 pin;
  124. ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
  125. if (ret)
  126. return ret;
  127. if (!pin)
  128. return 0;
  129. ret = of_irq_map_pci(dev, &oirq);
  130. if (ret)
  131. return ret;
  132. virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
  133. oirq.size);
  134. if (virq == 0)
  135. return -EINVAL;
  136. dev->irq = virq;
  137. return 0;
  138. }
  139. static void x86_of_pci_irq_disable(struct pci_dev *dev)
  140. {
  141. }
  142. void __cpuinit x86_of_pci_init(void)
  143. {
  144. struct device_node *np;
  145. pcibios_enable_irq = x86_of_pci_irq_enable;
  146. pcibios_disable_irq = x86_of_pci_irq_disable;
  147. for_each_node_by_type(np, "pci") {
  148. const void *prop;
  149. struct pci_bus *bus;
  150. unsigned int bus_min;
  151. struct device_node *child;
  152. prop = of_get_property(np, "bus-range", NULL);
  153. if (!prop)
  154. continue;
  155. bus_min = be32_to_cpup(prop);
  156. bus = pci_find_bus(0, bus_min);
  157. if (!bus) {
  158. printk(KERN_ERR "Can't find a node for bus %s.\n",
  159. np->full_name);
  160. continue;
  161. }
  162. if (bus->self)
  163. bus->self->dev.of_node = np;
  164. else
  165. bus->dev.of_node = np;
  166. for_each_child_of_node(np, child) {
  167. struct pci_dev *dev;
  168. u32 devfn;
  169. prop = of_get_property(child, "reg", NULL);
  170. if (!prop)
  171. continue;
  172. devfn = (be32_to_cpup(prop) >> 8) & 0xff;
  173. dev = pci_get_slot(bus, devfn);
  174. if (!dev)
  175. continue;
  176. dev->dev.of_node = child;
  177. pci_dev_put(dev);
  178. }
  179. }
  180. }
  181. #endif
  182. static void __init dtb_setup_hpet(void)
  183. {
  184. #ifdef CONFIG_HPET_TIMER
  185. struct device_node *dn;
  186. struct resource r;
  187. int ret;
  188. dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
  189. if (!dn)
  190. return;
  191. ret = of_address_to_resource(dn, 0, &r);
  192. if (ret) {
  193. WARN_ON(1);
  194. return;
  195. }
  196. hpet_address = r.start;
  197. #endif
  198. }
  199. static void __init dtb_lapic_setup(void)
  200. {
  201. #ifdef CONFIG_X86_LOCAL_APIC
  202. struct device_node *dn;
  203. struct resource r;
  204. int ret;
  205. dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
  206. if (!dn)
  207. return;
  208. ret = of_address_to_resource(dn, 0, &r);
  209. if (WARN_ON(ret))
  210. return;
  211. /* Did the boot loader setup the local APIC ? */
  212. if (!cpu_has_apic) {
  213. if (apic_force_enable(r.start))
  214. return;
  215. }
  216. smp_found_config = 1;
  217. pic_mode = 1;
  218. register_lapic_address(r.start);
  219. generic_processor_info(boot_cpu_physical_apicid,
  220. GET_APIC_VERSION(apic_read(APIC_LVR)));
  221. #endif
  222. }
  223. #ifdef CONFIG_X86_IO_APIC
  224. static unsigned int ioapic_id;
  225. static void __init dtb_add_ioapic(struct device_node *dn)
  226. {
  227. struct resource r;
  228. int ret;
  229. ret = of_address_to_resource(dn, 0, &r);
  230. if (ret) {
  231. printk(KERN_ERR "Can't obtain address from node %s.\n",
  232. dn->full_name);
  233. return;
  234. }
  235. mp_register_ioapic(++ioapic_id, r.start, gsi_top);
  236. }
  237. static void __init dtb_ioapic_setup(void)
  238. {
  239. struct device_node *dn;
  240. for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
  241. dtb_add_ioapic(dn);
  242. if (nr_ioapics) {
  243. of_ioapic = 1;
  244. return;
  245. }
  246. printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
  247. }
  248. #else
  249. static void __init dtb_ioapic_setup(void) {}
  250. #endif
  251. static void __init dtb_apic_setup(void)
  252. {
  253. dtb_lapic_setup();
  254. dtb_ioapic_setup();
  255. }
  256. #ifdef CONFIG_OF_FLATTREE
  257. static void __init x86_flattree_get_config(void)
  258. {
  259. u32 size, map_len;
  260. void *new_dtb;
  261. if (!initial_dtb)
  262. return;
  263. map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
  264. (u64)sizeof(struct boot_param_header));
  265. initial_boot_params = early_memremap(initial_dtb, map_len);
  266. size = be32_to_cpu(initial_boot_params->totalsize);
  267. if (map_len < size) {
  268. early_iounmap(initial_boot_params, map_len);
  269. initial_boot_params = early_memremap(initial_dtb, size);
  270. map_len = size;
  271. }
  272. new_dtb = alloc_bootmem(size);
  273. memcpy(new_dtb, initial_boot_params, size);
  274. early_iounmap(initial_boot_params, map_len);
  275. initial_boot_params = new_dtb;
  276. /* root level address cells */
  277. of_scan_flat_dt(early_init_dt_scan_root, NULL);
  278. unflatten_device_tree();
  279. }
  280. #else
  281. static inline void x86_flattree_get_config(void) { }
  282. #endif
  283. void __init x86_dtb_init(void)
  284. {
  285. x86_flattree_get_config();
  286. if (!of_have_populated_dt())
  287. return;
  288. dtb_setup_hpet();
  289. dtb_apic_setup();
  290. }
  291. #ifdef CONFIG_X86_IO_APIC
  292. struct of_ioapic_type {
  293. u32 out_type;
  294. u32 trigger;
  295. u32 polarity;
  296. };
  297. static struct of_ioapic_type of_ioapic_type[] =
  298. {
  299. {
  300. .out_type = IRQ_TYPE_EDGE_RISING,
  301. .trigger = IOAPIC_EDGE,
  302. .polarity = 1,
  303. },
  304. {
  305. .out_type = IRQ_TYPE_LEVEL_LOW,
  306. .trigger = IOAPIC_LEVEL,
  307. .polarity = 0,
  308. },
  309. {
  310. .out_type = IRQ_TYPE_LEVEL_HIGH,
  311. .trigger = IOAPIC_LEVEL,
  312. .polarity = 1,
  313. },
  314. {
  315. .out_type = IRQ_TYPE_EDGE_FALLING,
  316. .trigger = IOAPIC_EDGE,
  317. .polarity = 0,
  318. },
  319. };
  320. static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize,
  321. u32 *out_hwirq, u32 *out_type)
  322. {
  323. struct mp_ioapic_gsi *gsi_cfg;
  324. struct io_apic_irq_attr attr;
  325. struct of_ioapic_type *it;
  326. u32 line, idx, type;
  327. if (intsize < 2)
  328. return -EINVAL;
  329. line = *intspec;
  330. idx = (u32) id->priv;
  331. gsi_cfg = mp_ioapic_gsi_routing(idx);
  332. *out_hwirq = line + gsi_cfg->gsi_base;
  333. intspec++;
  334. type = *intspec;
  335. if (type >= ARRAY_SIZE(of_ioapic_type))
  336. return -EINVAL;
  337. it = of_ioapic_type + type;
  338. *out_type = it->out_type;
  339. set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
  340. return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr);
  341. }
  342. static void __init ioapic_add_ofnode(struct device_node *np)
  343. {
  344. struct resource r;
  345. int i, ret;
  346. ret = of_address_to_resource(np, 0, &r);
  347. if (ret) {
  348. printk(KERN_ERR "Failed to obtain address for %s\n",
  349. np->full_name);
  350. return;
  351. }
  352. for (i = 0; i < nr_ioapics; i++) {
  353. if (r.start == mpc_ioapic_addr(i)) {
  354. struct irq_domain *id;
  355. id = kzalloc(sizeof(*id), GFP_KERNEL);
  356. BUG_ON(!id);
  357. id->controller = np;
  358. id->xlate = ioapic_xlate;
  359. id->priv = (void *)i;
  360. add_interrupt_host(id);
  361. return;
  362. }
  363. }
  364. printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
  365. }
  366. void __init x86_add_irq_domains(void)
  367. {
  368. struct device_node *dp;
  369. if (!of_have_populated_dt())
  370. return;
  371. for_each_node_with_property(dp, "interrupt-controller") {
  372. if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
  373. ioapic_add_ofnode(dp);
  374. }
  375. }
  376. #else
  377. void __init x86_add_irq_domains(void) { }
  378. #endif