clock.c 11 KB

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  1. /* linux/arch/arm/plat-s3c24xx/clock.c
  2. *
  3. * Copyright 2004-2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C24XX Core clock control support
  7. *
  8. * Based on, and code from linux/arch/arm/mach-versatile/clock.c
  9. **
  10. ** Copyright (C) 2004 ARM Limited.
  11. ** Written by Deep Blue Solutions Limited.
  12. *
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  27. */
  28. #include <linux/init.h>
  29. #include <linux/module.h>
  30. #include <linux/kernel.h>
  31. #include <linux/list.h>
  32. #include <linux/errno.h>
  33. #include <linux/err.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/sysdev.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/ioport.h>
  38. #include <linux/clk.h>
  39. #include <linux/spinlock.h>
  40. #include <linux/io.h>
  41. #if defined(CONFIG_DEBUG_FS)
  42. #include <linux/debugfs.h>
  43. #endif
  44. #include <mach/hardware.h>
  45. #include <asm/irq.h>
  46. #include <plat/cpu-freq.h>
  47. #include <plat/clock.h>
  48. #include <plat/cpu.h>
  49. #include <linux/serial_core.h>
  50. #include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
  51. /* clock information */
  52. static LIST_HEAD(clocks);
  53. /* We originally used an mutex here, but some contexts (see resume)
  54. * are calling functions such as clk_set_parent() with IRQs disabled
  55. * causing an BUG to be triggered.
  56. */
  57. DEFINE_SPINLOCK(clocks_lock);
  58. /* enable and disable calls for use with the clk struct */
  59. static int clk_null_enable(struct clk *clk, int enable)
  60. {
  61. return 0;
  62. }
  63. static int dev_is_s3c_uart(struct device *dev)
  64. {
  65. struct platform_device **pdev = s3c24xx_uart_devs;
  66. int i;
  67. for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
  68. if (*pdev && dev == &(*pdev)->dev)
  69. return 1;
  70. return 0;
  71. }
  72. /*
  73. * Serial drivers call get_clock() very early, before platform bus
  74. * has been set up, this requires a special check to let them get
  75. * a proper clock
  76. */
  77. static int dev_is_platform_device(struct device *dev)
  78. {
  79. return dev->bus == &platform_bus_type ||
  80. (dev->bus == NULL && dev_is_s3c_uart(dev));
  81. }
  82. /* Clock API calls */
  83. struct clk *clk_get(struct device *dev, const char *id)
  84. {
  85. struct clk *p;
  86. struct clk *clk = ERR_PTR(-ENOENT);
  87. int idno;
  88. if (dev == NULL || !dev_is_platform_device(dev))
  89. idno = -1;
  90. else
  91. idno = to_platform_device(dev)->id;
  92. spin_lock(&clocks_lock);
  93. list_for_each_entry(p, &clocks, list) {
  94. if (p->id == idno &&
  95. strcmp(id, p->name) == 0 &&
  96. try_module_get(p->owner)) {
  97. clk = p;
  98. break;
  99. }
  100. }
  101. /* check for the case where a device was supplied, but the
  102. * clock that was being searched for is not device specific */
  103. if (IS_ERR(clk)) {
  104. list_for_each_entry(p, &clocks, list) {
  105. if (p->id == -1 && strcmp(id, p->name) == 0 &&
  106. try_module_get(p->owner)) {
  107. clk = p;
  108. break;
  109. }
  110. }
  111. }
  112. spin_unlock(&clocks_lock);
  113. return clk;
  114. }
  115. void clk_put(struct clk *clk)
  116. {
  117. module_put(clk->owner);
  118. }
  119. int clk_enable(struct clk *clk)
  120. {
  121. if (IS_ERR(clk) || clk == NULL)
  122. return -EINVAL;
  123. clk_enable(clk->parent);
  124. spin_lock(&clocks_lock);
  125. if ((clk->usage++) == 0)
  126. (clk->enable)(clk, 1);
  127. spin_unlock(&clocks_lock);
  128. return 0;
  129. }
  130. void clk_disable(struct clk *clk)
  131. {
  132. if (IS_ERR(clk) || clk == NULL)
  133. return;
  134. spin_lock(&clocks_lock);
  135. if ((--clk->usage) == 0)
  136. (clk->enable)(clk, 0);
  137. spin_unlock(&clocks_lock);
  138. clk_disable(clk->parent);
  139. }
  140. unsigned long clk_get_rate(struct clk *clk)
  141. {
  142. if (IS_ERR(clk))
  143. return 0;
  144. if (clk->rate != 0)
  145. return clk->rate;
  146. if (clk->ops != NULL && clk->ops->get_rate != NULL)
  147. return (clk->ops->get_rate)(clk);
  148. if (clk->parent != NULL)
  149. return clk_get_rate(clk->parent);
  150. return clk->rate;
  151. }
  152. long clk_round_rate(struct clk *clk, unsigned long rate)
  153. {
  154. if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
  155. return (clk->ops->round_rate)(clk, rate);
  156. return rate;
  157. }
  158. int clk_set_rate(struct clk *clk, unsigned long rate)
  159. {
  160. int ret;
  161. if (IS_ERR(clk))
  162. return -EINVAL;
  163. /* We do not default just do a clk->rate = rate as
  164. * the clock may have been made this way by choice.
  165. */
  166. WARN_ON(clk->ops == NULL);
  167. WARN_ON(clk->ops && clk->ops->set_rate == NULL);
  168. if (clk->ops == NULL || clk->ops->set_rate == NULL)
  169. return -EINVAL;
  170. spin_lock(&clocks_lock);
  171. ret = (clk->ops->set_rate)(clk, rate);
  172. spin_unlock(&clocks_lock);
  173. return ret;
  174. }
  175. struct clk *clk_get_parent(struct clk *clk)
  176. {
  177. return clk->parent;
  178. }
  179. int clk_set_parent(struct clk *clk, struct clk *parent)
  180. {
  181. int ret = 0;
  182. if (IS_ERR(clk))
  183. return -EINVAL;
  184. spin_lock(&clocks_lock);
  185. if (clk->ops && clk->ops->set_parent)
  186. ret = (clk->ops->set_parent)(clk, parent);
  187. spin_unlock(&clocks_lock);
  188. return ret;
  189. }
  190. EXPORT_SYMBOL(clk_get);
  191. EXPORT_SYMBOL(clk_put);
  192. EXPORT_SYMBOL(clk_enable);
  193. EXPORT_SYMBOL(clk_disable);
  194. EXPORT_SYMBOL(clk_get_rate);
  195. EXPORT_SYMBOL(clk_round_rate);
  196. EXPORT_SYMBOL(clk_set_rate);
  197. EXPORT_SYMBOL(clk_get_parent);
  198. EXPORT_SYMBOL(clk_set_parent);
  199. /* base clocks */
  200. int clk_default_setrate(struct clk *clk, unsigned long rate)
  201. {
  202. clk->rate = rate;
  203. return 0;
  204. }
  205. struct clk_ops clk_ops_def_setrate = {
  206. .set_rate = clk_default_setrate,
  207. };
  208. struct clk clk_xtal = {
  209. .name = "xtal",
  210. .id = -1,
  211. .rate = 0,
  212. .parent = NULL,
  213. .ctrlbit = 0,
  214. };
  215. struct clk clk_ext = {
  216. .name = "ext",
  217. .id = -1,
  218. };
  219. struct clk clk_epll = {
  220. .name = "epll",
  221. .id = -1,
  222. };
  223. struct clk clk_mpll = {
  224. .name = "mpll",
  225. .id = -1,
  226. .ops = &clk_ops_def_setrate,
  227. };
  228. struct clk clk_upll = {
  229. .name = "upll",
  230. .id = -1,
  231. .parent = NULL,
  232. .ctrlbit = 0,
  233. };
  234. struct clk clk_f = {
  235. .name = "fclk",
  236. .id = -1,
  237. .rate = 0,
  238. .parent = &clk_mpll,
  239. .ctrlbit = 0,
  240. };
  241. struct clk clk_h = {
  242. .name = "hclk",
  243. .id = -1,
  244. .rate = 0,
  245. .parent = NULL,
  246. .ctrlbit = 0,
  247. .ops = &clk_ops_def_setrate,
  248. };
  249. struct clk clk_p = {
  250. .name = "pclk",
  251. .id = -1,
  252. .rate = 0,
  253. .parent = NULL,
  254. .ctrlbit = 0,
  255. .ops = &clk_ops_def_setrate,
  256. };
  257. struct clk clk_usb_bus = {
  258. .name = "usb-bus",
  259. .id = -1,
  260. .rate = 0,
  261. .parent = &clk_upll,
  262. };
  263. struct clk s3c24xx_uclk = {
  264. .name = "uclk",
  265. .id = -1,
  266. };
  267. /* initialise the clock system */
  268. /**
  269. * s3c24xx_register_clock() - register a clock
  270. * @clk: The clock to register
  271. *
  272. * Add the specified clock to the list of clocks known by the system.
  273. */
  274. int s3c24xx_register_clock(struct clk *clk)
  275. {
  276. if (clk->enable == NULL)
  277. clk->enable = clk_null_enable;
  278. /* add to the list of available clocks */
  279. /* Quick check to see if this clock has already been registered. */
  280. BUG_ON(clk->list.prev != clk->list.next);
  281. spin_lock(&clocks_lock);
  282. list_add(&clk->list, &clocks);
  283. spin_unlock(&clocks_lock);
  284. return 0;
  285. }
  286. /**
  287. * s3c24xx_register_clocks() - register an array of clock pointers
  288. * @clks: Pointer to an array of struct clk pointers
  289. * @nr_clks: The number of clocks in the @clks array.
  290. *
  291. * Call s3c24xx_register_clock() for all the clock pointers contained
  292. * in the @clks list. Returns the number of failures.
  293. */
  294. int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
  295. {
  296. int fails = 0;
  297. for (; nr_clks > 0; nr_clks--, clks++) {
  298. if (s3c24xx_register_clock(*clks) < 0) {
  299. struct clk *clk = *clks;
  300. printk(KERN_ERR "%s: failed to register %p: %s\n",
  301. __func__, clk, clk->name);
  302. fails++;
  303. }
  304. }
  305. return fails;
  306. }
  307. /**
  308. * s3c_register_clocks() - register an array of clocks
  309. * @clkp: Pointer to the first clock in the array.
  310. * @nr_clks: Number of clocks to register.
  311. *
  312. * Call s3c24xx_register_clock() on the @clkp array given, printing an
  313. * error if it fails to register the clock (unlikely).
  314. */
  315. void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
  316. {
  317. int ret;
  318. for (; nr_clks > 0; nr_clks--, clkp++) {
  319. ret = s3c24xx_register_clock(clkp);
  320. if (ret < 0) {
  321. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  322. clkp->name, ret);
  323. }
  324. }
  325. }
  326. /**
  327. * s3c_disable_clocks() - disable an array of clocks
  328. * @clkp: Pointer to the first clock in the array.
  329. * @nr_clks: Number of clocks to register.
  330. *
  331. * for internal use only at initialisation time. disable the clocks in the
  332. * @clkp array.
  333. */
  334. void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
  335. {
  336. for (; nr_clks > 0; nr_clks--, clkp++)
  337. (clkp->enable)(clkp, 0);
  338. }
  339. /* initialise all the clocks */
  340. int __init s3c24xx_register_baseclocks(unsigned long xtal)
  341. {
  342. printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
  343. clk_xtal.rate = xtal;
  344. /* register our clocks */
  345. if (s3c24xx_register_clock(&clk_xtal) < 0)
  346. printk(KERN_ERR "failed to register master xtal\n");
  347. if (s3c24xx_register_clock(&clk_mpll) < 0)
  348. printk(KERN_ERR "failed to register mpll clock\n");
  349. if (s3c24xx_register_clock(&clk_upll) < 0)
  350. printk(KERN_ERR "failed to register upll clock\n");
  351. if (s3c24xx_register_clock(&clk_f) < 0)
  352. printk(KERN_ERR "failed to register cpu fclk\n");
  353. if (s3c24xx_register_clock(&clk_h) < 0)
  354. printk(KERN_ERR "failed to register cpu hclk\n");
  355. if (s3c24xx_register_clock(&clk_p) < 0)
  356. printk(KERN_ERR "failed to register cpu pclk\n");
  357. return 0;
  358. }
  359. #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
  360. /* debugfs support to trace clock tree hierarchy and attributes */
  361. static struct dentry *clk_debugfs_root;
  362. static int clk_debugfs_register_one(struct clk *c)
  363. {
  364. int err;
  365. struct dentry *d, *child, *child_tmp;
  366. struct clk *pa = c->parent;
  367. char s[255];
  368. char *p = s;
  369. p += sprintf(p, "%s", c->name);
  370. if (c->id >= 0)
  371. sprintf(p, ":%d", c->id);
  372. d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
  373. if (!d)
  374. return -ENOMEM;
  375. c->dent = d;
  376. d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
  377. if (!d) {
  378. err = -ENOMEM;
  379. goto err_out;
  380. }
  381. d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
  382. if (!d) {
  383. err = -ENOMEM;
  384. goto err_out;
  385. }
  386. return 0;
  387. err_out:
  388. d = c->dent;
  389. list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
  390. debugfs_remove(child);
  391. debugfs_remove(c->dent);
  392. return err;
  393. }
  394. static int clk_debugfs_register(struct clk *c)
  395. {
  396. int err;
  397. struct clk *pa = c->parent;
  398. if (pa && !pa->dent) {
  399. err = clk_debugfs_register(pa);
  400. if (err)
  401. return err;
  402. }
  403. if (!c->dent) {
  404. err = clk_debugfs_register_one(c);
  405. if (err)
  406. return err;
  407. }
  408. return 0;
  409. }
  410. static int __init clk_debugfs_init(void)
  411. {
  412. struct clk *c;
  413. struct dentry *d;
  414. int err;
  415. d = debugfs_create_dir("clock", NULL);
  416. if (!d)
  417. return -ENOMEM;
  418. clk_debugfs_root = d;
  419. list_for_each_entry(c, &clocks, list) {
  420. err = clk_debugfs_register(c);
  421. if (err)
  422. goto err_out;
  423. }
  424. return 0;
  425. err_out:
  426. debugfs_remove_recursive(clk_debugfs_root);
  427. return err;
  428. }
  429. late_initcall(clk_debugfs_init);
  430. #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */