setup-sdhci.c 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566
  1. /* linux/arch/arm/mach-s5pc100/setup-sdhci.c
  2. *
  3. * Copyright 2008 Samsung Electronics
  4. *
  5. * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
  6. *
  7. * Based on mach-s3c6410/setup-sdhci.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/io.h>
  18. #include <linux/mmc/card.h>
  19. #include <linux/mmc/host.h>
  20. #include <plat/regs-sdhci.h>
  21. #include <plat/sdhci.h>
  22. /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
  23. char *s5pc100_hsmmc_clksrcs[4] = {
  24. [0] = "hsmmc", /* HCLK */
  25. /* [1] = "hsmmc", - duplicate HCLK entry */
  26. [2] = "sclk_mmc", /* mmc_bus */
  27. /* [3] = "48m", - note not successfully used yet */
  28. };
  29. void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
  30. void __iomem *r,
  31. struct mmc_ios *ios,
  32. struct mmc_card *card)
  33. {
  34. u32 ctrl2, ctrl3;
  35. /* don't need to alter anything according to card-type */
  36. writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
  37. ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
  38. ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
  39. ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
  40. S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
  41. S3C_SDHCI_CTRL2_ENFBCLKRX |
  42. S3C_SDHCI_CTRL2_DFCNT_NONE |
  43. S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
  44. if (ios->clock < 25 * 1000000)
  45. ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
  46. S3C_SDHCI_CTRL3_FCSEL2 |
  47. S3C_SDHCI_CTRL3_FCSEL1 |
  48. S3C_SDHCI_CTRL3_FCSEL0);
  49. else
  50. ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
  51. writel(ctrl2, r + S3C_SDHCI_CONTROL2);
  52. writel(ctrl3, r + S3C_SDHCI_CONTROL3);
  53. }