s3c244x.c 4.5 KB

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  1. /* linux/arch/arm/plat-s3c24xx/s3c244x.c
  2. *
  3. * Copyright (c) 2004-2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/init.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/sysdev.h>
  21. #include <linux/syscore_ops.h>
  22. #include <linux/clk.h>
  23. #include <linux/io.h>
  24. #include <asm/mach/arch.h>
  25. #include <asm/mach/map.h>
  26. #include <asm/mach/irq.h>
  27. #include <mach/hardware.h>
  28. #include <asm/irq.h>
  29. #include <plat/cpu-freq.h>
  30. #include <mach/regs-clock.h>
  31. #include <plat/regs-serial.h>
  32. #include <mach/regs-gpio.h>
  33. #include <mach/regs-gpioj.h>
  34. #include <mach/regs-dsc.h>
  35. #include <plat/s3c2410.h>
  36. #include <plat/s3c244x.h>
  37. #include <plat/clock.h>
  38. #include <plat/devs.h>
  39. #include <plat/cpu.h>
  40. #include <plat/pm.h>
  41. #include <plat/pll.h>
  42. #include <plat/nand-core.h>
  43. static struct map_desc s3c244x_iodesc[] __initdata = {
  44. IODESC_ENT(CLKPWR),
  45. IODESC_ENT(TIMER),
  46. IODESC_ENT(WATCHDOG),
  47. };
  48. /* uart initialisation */
  49. void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  50. {
  51. s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
  52. }
  53. void __init s3c244x_map_io(void)
  54. {
  55. /* register our io-tables */
  56. iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
  57. /* rename any peripherals used differing from the s3c2410 */
  58. s3c_device_sdi.name = "s3c2440-sdi";
  59. s3c_device_i2c0.name = "s3c2440-i2c";
  60. s3c_nand_setname("s3c2440-nand");
  61. s3c_device_ts.name = "s3c2440-ts";
  62. s3c_device_usbgadget.name = "s3c2440-usbgadget";
  63. }
  64. void __init_or_cpufreq s3c244x_setup_clocks(void)
  65. {
  66. struct clk *xtal_clk;
  67. unsigned long clkdiv;
  68. unsigned long camdiv;
  69. unsigned long xtal;
  70. unsigned long hclk, fclk, pclk;
  71. int hdiv = 1;
  72. xtal_clk = clk_get(NULL, "xtal");
  73. xtal = clk_get_rate(xtal_clk);
  74. clk_put(xtal_clk);
  75. fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
  76. clkdiv = __raw_readl(S3C2410_CLKDIVN);
  77. camdiv = __raw_readl(S3C2440_CAMDIVN);
  78. /* work out clock scalings */
  79. switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
  80. case S3C2440_CLKDIVN_HDIVN_1:
  81. hdiv = 1;
  82. break;
  83. case S3C2440_CLKDIVN_HDIVN_2:
  84. hdiv = 2;
  85. break;
  86. case S3C2440_CLKDIVN_HDIVN_4_8:
  87. hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
  88. break;
  89. case S3C2440_CLKDIVN_HDIVN_3_6:
  90. hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
  91. break;
  92. }
  93. hclk = fclk / hdiv;
  94. pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
  95. /* print brief summary of clocks, etc */
  96. printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
  97. print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
  98. s3c24xx_setup_clocks(fclk, hclk, pclk);
  99. }
  100. void __init s3c244x_init_clocks(int xtal)
  101. {
  102. /* initialise the clocks here, to allow other things like the
  103. * console to use them, and to add new ones after the initialisation
  104. */
  105. s3c24xx_register_baseclocks(xtal);
  106. s3c244x_setup_clocks();
  107. s3c2410_baseclk_add();
  108. }
  109. /* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
  110. struct sysdev_class s3c2440_sysclass = {
  111. .name = "s3c2440-core",
  112. };
  113. struct sysdev_class s3c2442_sysclass = {
  114. .name = "s3c2442-core",
  115. };
  116. /* need to register class before we actually register the device, and
  117. * we also need to ensure that it has been initialised before any of the
  118. * drivers even try to use it (even if not on an s3c2440 based system)
  119. * as a driver which may support both 2410 and 2440 may try and use it.
  120. */
  121. static int __init s3c2440_core_init(void)
  122. {
  123. return sysdev_class_register(&s3c2440_sysclass);
  124. }
  125. core_initcall(s3c2440_core_init);
  126. static int __init s3c2442_core_init(void)
  127. {
  128. return sysdev_class_register(&s3c2442_sysclass);
  129. }
  130. core_initcall(s3c2442_core_init);
  131. #ifdef CONFIG_PM
  132. static struct sleep_save s3c244x_sleep[] = {
  133. SAVE_ITEM(S3C2440_DSC0),
  134. SAVE_ITEM(S3C2440_DSC1),
  135. SAVE_ITEM(S3C2440_GPJDAT),
  136. SAVE_ITEM(S3C2440_GPJCON),
  137. SAVE_ITEM(S3C2440_GPJUP)
  138. };
  139. static int s3c244x_suspend(void)
  140. {
  141. s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
  142. return 0;
  143. }
  144. static void s3c244x_resume(void)
  145. {
  146. s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
  147. }
  148. #else
  149. #define s3c244x_suspend NULL
  150. #define s3c244x_resume NULL
  151. #endif
  152. struct syscore_ops s3c244x_pm_syscore_ops = {
  153. .suspend = s3c244x_suspend,
  154. .resume = s3c244x_resume,
  155. };