ab8500-gpio.c 13 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2011
  3. *
  4. * Author: BIBEK BASU <bibek.basu@stericsson.com>
  5. * License terms: GNU General Public License (GPL) version 2
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include <linux/slab.h>
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/err.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/slab.h>
  19. #include <linux/gpio.h>
  20. #include <linux/irq.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/mfd/ab8500.h>
  23. #include <linux/mfd/abx500.h>
  24. #include <linux/mfd/ab8500/gpio.h>
  25. /*
  26. * GPIO registers offset
  27. * Bank: 0x10
  28. */
  29. #define AB8500_GPIO_SEL1_REG 0x00
  30. #define AB8500_GPIO_SEL2_REG 0x01
  31. #define AB8500_GPIO_SEL3_REG 0x02
  32. #define AB8500_GPIO_SEL4_REG 0x03
  33. #define AB8500_GPIO_SEL5_REG 0x04
  34. #define AB8500_GPIO_SEL6_REG 0x05
  35. #define AB8500_GPIO_DIR1_REG 0x10
  36. #define AB8500_GPIO_DIR2_REG 0x11
  37. #define AB8500_GPIO_DIR3_REG 0x12
  38. #define AB8500_GPIO_DIR4_REG 0x13
  39. #define AB8500_GPIO_DIR5_REG 0x14
  40. #define AB8500_GPIO_DIR6_REG 0x15
  41. #define AB8500_GPIO_OUT1_REG 0x20
  42. #define AB8500_GPIO_OUT2_REG 0x21
  43. #define AB8500_GPIO_OUT3_REG 0x22
  44. #define AB8500_GPIO_OUT4_REG 0x23
  45. #define AB8500_GPIO_OUT5_REG 0x24
  46. #define AB8500_GPIO_OUT6_REG 0x25
  47. #define AB8500_GPIO_PUD1_REG 0x30
  48. #define AB8500_GPIO_PUD2_REG 0x31
  49. #define AB8500_GPIO_PUD3_REG 0x32
  50. #define AB8500_GPIO_PUD4_REG 0x33
  51. #define AB8500_GPIO_PUD5_REG 0x34
  52. #define AB8500_GPIO_PUD6_REG 0x35
  53. #define AB8500_GPIO_IN1_REG 0x40
  54. #define AB8500_GPIO_IN2_REG 0x41
  55. #define AB8500_GPIO_IN3_REG 0x42
  56. #define AB8500_GPIO_IN4_REG 0x43
  57. #define AB8500_GPIO_IN5_REG 0x44
  58. #define AB8500_GPIO_IN6_REG 0x45
  59. #define AB8500_GPIO_ALTFUN_REG 0x45
  60. #define ALTFUN_REG_INDEX 6
  61. #define AB8500_NUM_GPIO 42
  62. #define AB8500_NUM_VIR_GPIO_IRQ 16
  63. enum ab8500_gpio_action {
  64. NONE,
  65. STARTUP,
  66. SHUTDOWN,
  67. MASK,
  68. UNMASK
  69. };
  70. struct ab8500_gpio {
  71. struct gpio_chip chip;
  72. struct ab8500 *parent;
  73. struct device *dev;
  74. struct mutex lock;
  75. u32 irq_base;
  76. enum ab8500_gpio_action irq_action;
  77. u16 rising;
  78. u16 falling;
  79. };
  80. /**
  81. * to_ab8500_gpio() - get the pointer to ab8500_gpio
  82. * @chip: Member of the structure ab8500_gpio
  83. */
  84. static inline struct ab8500_gpio *to_ab8500_gpio(struct gpio_chip *chip)
  85. {
  86. return container_of(chip, struct ab8500_gpio, chip);
  87. }
  88. static int ab8500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
  89. unsigned offset, int val)
  90. {
  91. struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
  92. u8 pos = offset % 8;
  93. int ret;
  94. reg = reg + (offset / 8);
  95. ret = abx500_mask_and_set_register_interruptible(ab8500_gpio->dev,
  96. AB8500_MISC, reg, 1 << pos, val << pos);
  97. if (ret < 0)
  98. dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
  99. return ret;
  100. }
  101. /**
  102. * ab8500_gpio_get() - Get the particular GPIO value
  103. * @chip: Gpio device
  104. * @offset: GPIO number to read
  105. */
  106. static int ab8500_gpio_get(struct gpio_chip *chip, unsigned offset)
  107. {
  108. struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
  109. u8 mask = 1 << (offset % 8);
  110. u8 reg = AB8500_GPIO_OUT1_REG + (offset / 8);
  111. int ret;
  112. u8 data;
  113. ret = abx500_get_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
  114. reg, &data);
  115. if (ret < 0) {
  116. dev_err(ab8500_gpio->dev, "%s read failed\n", __func__);
  117. return ret;
  118. }
  119. return (data & mask) >> (offset % 8);
  120. }
  121. static void ab8500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  122. {
  123. struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
  124. int ret;
  125. /* Write the data */
  126. ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, 1);
  127. if (ret < 0)
  128. dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
  129. }
  130. static int ab8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  131. int val)
  132. {
  133. int ret;
  134. /* set direction as output */
  135. ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
  136. if (ret < 0)
  137. return ret;
  138. /* disable pull down */
  139. ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
  140. if (ret < 0)
  141. return ret;
  142. /* set the output as 1 or 0 */
  143. return ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
  144. }
  145. static int ab8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  146. {
  147. /* set the register as input */
  148. return ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
  149. }
  150. static int ab8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  151. {
  152. /*
  153. * Only some GPIOs are interrupt capable, and they are
  154. * organized in discontiguous clusters:
  155. *
  156. * GPIO6 to GPIO13
  157. * GPIO24 and GPIO25
  158. * GPIO36 to GPIO41
  159. */
  160. static struct ab8500_gpio_irq_cluster {
  161. int start;
  162. int end;
  163. } clusters[] = {
  164. {.start = 6, .end = 13},
  165. {.start = 24, .end = 25},
  166. {.start = 36, .end = 41},
  167. };
  168. struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
  169. int base = ab8500_gpio->irq_base;
  170. int i;
  171. for (i = 0; i < ARRAY_SIZE(clusters); i++) {
  172. struct ab8500_gpio_irq_cluster *cluster = &clusters[i];
  173. if (offset >= cluster->start && offset <= cluster->end)
  174. return base + offset - cluster->start;
  175. /* Advance by the number of gpios in this cluster */
  176. base += cluster->end - cluster->start + 1;
  177. }
  178. return -EINVAL;
  179. }
  180. static struct gpio_chip ab8500gpio_chip = {
  181. .label = "ab8500_gpio",
  182. .owner = THIS_MODULE,
  183. .direction_input = ab8500_gpio_direction_input,
  184. .get = ab8500_gpio_get,
  185. .direction_output = ab8500_gpio_direction_output,
  186. .set = ab8500_gpio_set,
  187. .to_irq = ab8500_gpio_to_irq,
  188. };
  189. static unsigned int irq_to_rising(unsigned int irq)
  190. {
  191. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  192. int offset = irq - ab8500_gpio->irq_base;
  193. int new_irq = offset + AB8500_INT_GPIO6R
  194. + ab8500_gpio->parent->irq_base;
  195. return new_irq;
  196. }
  197. static unsigned int irq_to_falling(unsigned int irq)
  198. {
  199. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  200. int offset = irq - ab8500_gpio->irq_base;
  201. int new_irq = offset + AB8500_INT_GPIO6F
  202. + ab8500_gpio->parent->irq_base;
  203. return new_irq;
  204. }
  205. static unsigned int rising_to_irq(unsigned int irq, void *dev)
  206. {
  207. struct ab8500_gpio *ab8500_gpio = dev;
  208. int offset = irq - AB8500_INT_GPIO6R
  209. - ab8500_gpio->parent->irq_base ;
  210. int new_irq = offset + ab8500_gpio->irq_base;
  211. return new_irq;
  212. }
  213. static unsigned int falling_to_irq(unsigned int irq, void *dev)
  214. {
  215. struct ab8500_gpio *ab8500_gpio = dev;
  216. int offset = irq - AB8500_INT_GPIO6F
  217. - ab8500_gpio->parent->irq_base ;
  218. int new_irq = offset + ab8500_gpio->irq_base;
  219. return new_irq;
  220. }
  221. /*
  222. * IRQ handler
  223. */
  224. static irqreturn_t handle_rising(int irq, void *dev)
  225. {
  226. handle_nested_irq(rising_to_irq(irq , dev));
  227. return IRQ_HANDLED;
  228. }
  229. static irqreturn_t handle_falling(int irq, void *dev)
  230. {
  231. handle_nested_irq(falling_to_irq(irq, dev));
  232. return IRQ_HANDLED;
  233. }
  234. static void ab8500_gpio_irq_lock(unsigned int irq)
  235. {
  236. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  237. mutex_lock(&ab8500_gpio->lock);
  238. }
  239. static void ab8500_gpio_irq_sync_unlock(unsigned int irq)
  240. {
  241. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  242. int offset = irq - ab8500_gpio->irq_base;
  243. bool rising = ab8500_gpio->rising & BIT(offset);
  244. bool falling = ab8500_gpio->falling & BIT(offset);
  245. int ret;
  246. switch (ab8500_gpio->irq_action) {
  247. case STARTUP:
  248. if (rising)
  249. ret = request_threaded_irq(irq_to_rising(irq),
  250. NULL, handle_rising,
  251. IRQF_TRIGGER_RISING,
  252. "ab8500-gpio-r", ab8500_gpio);
  253. if (falling)
  254. ret = request_threaded_irq(irq_to_falling(irq),
  255. NULL, handle_falling,
  256. IRQF_TRIGGER_FALLING,
  257. "ab8500-gpio-f", ab8500_gpio);
  258. break;
  259. case SHUTDOWN:
  260. if (rising)
  261. free_irq(irq_to_rising(irq), ab8500_gpio);
  262. if (falling)
  263. free_irq(irq_to_falling(irq), ab8500_gpio);
  264. break;
  265. case MASK:
  266. if (rising)
  267. disable_irq(irq_to_rising(irq));
  268. if (falling)
  269. disable_irq(irq_to_falling(irq));
  270. break;
  271. case UNMASK:
  272. if (rising)
  273. enable_irq(irq_to_rising(irq));
  274. if (falling)
  275. enable_irq(irq_to_falling(irq));
  276. break;
  277. case NONE:
  278. break;
  279. }
  280. ab8500_gpio->irq_action = NONE;
  281. ab8500_gpio->rising &= ~(BIT(offset));
  282. ab8500_gpio->falling &= ~(BIT(offset));
  283. mutex_unlock(&ab8500_gpio->lock);
  284. }
  285. static void ab8500_gpio_irq_mask(unsigned int irq)
  286. {
  287. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  288. ab8500_gpio->irq_action = MASK;
  289. }
  290. static void ab8500_gpio_irq_unmask(unsigned int irq)
  291. {
  292. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  293. ab8500_gpio->irq_action = UNMASK;
  294. }
  295. static int ab8500_gpio_irq_set_type(unsigned int irq, unsigned int type)
  296. {
  297. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  298. int offset = irq - ab8500_gpio->irq_base;
  299. if (type == IRQ_TYPE_EDGE_BOTH) {
  300. ab8500_gpio->rising = BIT(offset);
  301. ab8500_gpio->falling = BIT(offset);
  302. } else if (type == IRQ_TYPE_EDGE_RISING) {
  303. ab8500_gpio->rising = BIT(offset);
  304. } else {
  305. ab8500_gpio->falling = BIT(offset);
  306. }
  307. return 0;
  308. }
  309. unsigned int ab8500_gpio_irq_startup(unsigned int irq)
  310. {
  311. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  312. ab8500_gpio->irq_action = STARTUP;
  313. return 0;
  314. }
  315. void ab8500_gpio_irq_shutdown(unsigned int irq)
  316. {
  317. struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
  318. ab8500_gpio->irq_action = SHUTDOWN;
  319. }
  320. static struct irq_chip ab8500_gpio_irq_chip = {
  321. .name = "ab8500-gpio",
  322. .startup = ab8500_gpio_irq_startup,
  323. .shutdown = ab8500_gpio_irq_shutdown,
  324. .bus_lock = ab8500_gpio_irq_lock,
  325. .bus_sync_unlock = ab8500_gpio_irq_sync_unlock,
  326. .mask = ab8500_gpio_irq_mask,
  327. .unmask = ab8500_gpio_irq_unmask,
  328. .set_type = ab8500_gpio_irq_set_type,
  329. };
  330. static int ab8500_gpio_irq_init(struct ab8500_gpio *ab8500_gpio)
  331. {
  332. u32 base = ab8500_gpio->irq_base;
  333. int irq;
  334. for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) {
  335. set_irq_chip_data(irq, ab8500_gpio);
  336. set_irq_chip_and_handler(irq, &ab8500_gpio_irq_chip,
  337. handle_simple_irq);
  338. set_irq_nested_thread(irq, 1);
  339. #ifdef CONFIG_ARM
  340. set_irq_flags(irq, IRQF_VALID);
  341. #else
  342. set_irq_noprobe(irq);
  343. #endif
  344. }
  345. return 0;
  346. }
  347. static void ab8500_gpio_irq_remove(struct ab8500_gpio *ab8500_gpio)
  348. {
  349. int base = ab8500_gpio->irq_base;
  350. int irq;
  351. for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) {
  352. #ifdef CONFIG_ARM
  353. set_irq_flags(irq, 0);
  354. #endif
  355. set_irq_chip_and_handler(irq, NULL, NULL);
  356. set_irq_chip_data(irq, NULL);
  357. }
  358. }
  359. static int __devinit ab8500_gpio_probe(struct platform_device *pdev)
  360. {
  361. struct ab8500_platform_data *ab8500_pdata =
  362. dev_get_platdata(pdev->dev.parent);
  363. struct ab8500_gpio_platform_data *pdata;
  364. struct ab8500_gpio *ab8500_gpio;
  365. int ret;
  366. int i;
  367. pdata = ab8500_pdata->gpio;
  368. if (!pdata) {
  369. dev_err(&pdev->dev, "gpio platform data missing\n");
  370. return -ENODEV;
  371. }
  372. ab8500_gpio = kzalloc(sizeof(struct ab8500_gpio), GFP_KERNEL);
  373. if (ab8500_gpio == NULL) {
  374. dev_err(&pdev->dev, "failed to allocate memory\n");
  375. return -ENOMEM;
  376. }
  377. ab8500_gpio->dev = &pdev->dev;
  378. ab8500_gpio->parent = dev_get_drvdata(pdev->dev.parent);
  379. ab8500_gpio->chip = ab8500gpio_chip;
  380. ab8500_gpio->chip.ngpio = AB8500_NUM_GPIO;
  381. ab8500_gpio->chip.dev = &pdev->dev;
  382. ab8500_gpio->chip.base = pdata->gpio_base;
  383. ab8500_gpio->irq_base = pdata->irq_base;
  384. /* initialize the lock */
  385. mutex_init(&ab8500_gpio->lock);
  386. /*
  387. * AB8500 core will handle and clear the IRQ
  388. * configre GPIO based on config-reg value.
  389. * These values are for selecting the PINs as
  390. * GPIO or alternate function
  391. */
  392. for (i = AB8500_GPIO_SEL1_REG; i <= AB8500_GPIO_SEL6_REG; i++) {
  393. ret = abx500_set_register_interruptible(ab8500_gpio->dev,
  394. AB8500_MISC, i,
  395. pdata->config_reg[i]);
  396. if (ret < 0)
  397. goto out_free;
  398. }
  399. ret = abx500_set_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
  400. AB8500_GPIO_ALTFUN_REG,
  401. pdata->config_reg[ALTFUN_REG_INDEX]);
  402. if (ret < 0)
  403. goto out_free;
  404. ret = ab8500_gpio_irq_init(ab8500_gpio);
  405. if (ret)
  406. goto out_free;
  407. ret = gpiochip_add(&ab8500_gpio->chip);
  408. if (ret) {
  409. dev_err(&pdev->dev, "unable to add gpiochip: %d\n",
  410. ret);
  411. goto out_rem_irq;
  412. }
  413. platform_set_drvdata(pdev, ab8500_gpio);
  414. return 0;
  415. out_rem_irq:
  416. ab8500_gpio_irq_remove(ab8500_gpio);
  417. out_free:
  418. mutex_destroy(&ab8500_gpio->lock);
  419. kfree(ab8500_gpio);
  420. return ret;
  421. }
  422. /*
  423. * ab8500_gpio_remove() - remove Ab8500-gpio driver
  424. * @pdev : Platform device registered
  425. */
  426. static int __devexit ab8500_gpio_remove(struct platform_device *pdev)
  427. {
  428. struct ab8500_gpio *ab8500_gpio = platform_get_drvdata(pdev);
  429. int ret;
  430. ret = gpiochip_remove(&ab8500_gpio->chip);
  431. if (ret < 0) {
  432. dev_err(ab8500_gpio->dev, "unable to remove gpiochip: %d\n",
  433. ret);
  434. return ret;
  435. }
  436. platform_set_drvdata(pdev, NULL);
  437. mutex_destroy(&ab8500_gpio->lock);
  438. kfree(ab8500_gpio);
  439. return 0;
  440. }
  441. static struct platform_driver ab8500_gpio_driver = {
  442. .driver = {
  443. .name = "ab8500-gpio",
  444. .owner = THIS_MODULE,
  445. },
  446. .probe = ab8500_gpio_probe,
  447. .remove = __devexit_p(ab8500_gpio_remove),
  448. };
  449. static int __init ab8500_gpio_init(void)
  450. {
  451. return platform_driver_register(&ab8500_gpio_driver);
  452. }
  453. arch_initcall(ab8500_gpio_init);
  454. static void __exit ab8500_gpio_exit(void)
  455. {
  456. platform_driver_unregister(&ab8500_gpio_driver);
  457. }
  458. module_exit(ab8500_gpio_exit);
  459. MODULE_AUTHOR("BIBEK BASU <bibek.basu@stericsson.com>");
  460. MODULE_DESCRIPTION("Driver allows to use AB8500 unused pins to be used as GPIO");
  461. MODULE_ALIAS("AB8500 GPIO driver");
  462. MODULE_LICENSE("GPL v2");