tegra2_emc.c 4.1 KB

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  1. /*
  2. * Copyright (C) 2011 Google, Inc.
  3. *
  4. * Author:
  5. * Colin Cross <ccross@android.com>
  6. *
  7. * This software is licensed under the terms of the GNU General Public
  8. * License version 2, as published by the Free Software Foundation, and
  9. * may be copied, distributed, and modified under those terms.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/io.h>
  21. #include <linux/module.h>
  22. #include <mach/iomap.h>
  23. #include "tegra2_emc.h"
  24. #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
  25. static bool emc_enable = true;
  26. #else
  27. static bool emc_enable;
  28. #endif
  29. module_param(emc_enable, bool, 0644);
  30. static void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
  31. static const struct tegra_emc_table *tegra_emc_table;
  32. static int tegra_emc_table_size;
  33. static inline void emc_writel(u32 val, unsigned long addr)
  34. {
  35. writel(val, emc + addr);
  36. }
  37. static inline u32 emc_readl(unsigned long addr)
  38. {
  39. return readl(emc + addr);
  40. }
  41. static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
  42. 0x2c, /* RC */
  43. 0x30, /* RFC */
  44. 0x34, /* RAS */
  45. 0x38, /* RP */
  46. 0x3c, /* R2W */
  47. 0x40, /* W2R */
  48. 0x44, /* R2P */
  49. 0x48, /* W2P */
  50. 0x4c, /* RD_RCD */
  51. 0x50, /* WR_RCD */
  52. 0x54, /* RRD */
  53. 0x58, /* REXT */
  54. 0x5c, /* WDV */
  55. 0x60, /* QUSE */
  56. 0x64, /* QRST */
  57. 0x68, /* QSAFE */
  58. 0x6c, /* RDV */
  59. 0x70, /* REFRESH */
  60. 0x74, /* BURST_REFRESH_NUM */
  61. 0x78, /* PDEX2WR */
  62. 0x7c, /* PDEX2RD */
  63. 0x80, /* PCHG2PDEN */
  64. 0x84, /* ACT2PDEN */
  65. 0x88, /* AR2PDEN */
  66. 0x8c, /* RW2PDEN */
  67. 0x90, /* TXSR */
  68. 0x94, /* TCKE */
  69. 0x98, /* TFAW */
  70. 0x9c, /* TRPAB */
  71. 0xa0, /* TCLKSTABLE */
  72. 0xa4, /* TCLKSTOP */
  73. 0xa8, /* TREFBW */
  74. 0xac, /* QUSE_EXTRA */
  75. 0x114, /* FBIO_CFG6 */
  76. 0xb0, /* ODT_WRITE */
  77. 0xb4, /* ODT_READ */
  78. 0x104, /* FBIO_CFG5 */
  79. 0x2bc, /* CFG_DIG_DLL */
  80. 0x2c0, /* DLL_XFORM_DQS */
  81. 0x2c4, /* DLL_XFORM_QUSE */
  82. 0x2e0, /* ZCAL_REF_CNT */
  83. 0x2e4, /* ZCAL_WAIT_CNT */
  84. 0x2a8, /* AUTO_CAL_INTERVAL */
  85. 0x2d0, /* CFG_CLKTRIM_0 */
  86. 0x2d4, /* CFG_CLKTRIM_1 */
  87. 0x2d8, /* CFG_CLKTRIM_2 */
  88. };
  89. /* Select the closest EMC rate that is higher than the requested rate */
  90. long tegra_emc_round_rate(unsigned long rate)
  91. {
  92. int i;
  93. int best = -1;
  94. unsigned long distance = ULONG_MAX;
  95. if (!tegra_emc_table)
  96. return -EINVAL;
  97. if (!emc_enable)
  98. return -EINVAL;
  99. pr_debug("%s: %lu\n", __func__, rate);
  100. /*
  101. * The EMC clock rate is twice the bus rate, and the bus rate is
  102. * measured in kHz
  103. */
  104. rate = rate / 2 / 1000;
  105. for (i = 0; i < tegra_emc_table_size; i++) {
  106. if (tegra_emc_table[i].rate >= rate &&
  107. (tegra_emc_table[i].rate - rate) < distance) {
  108. distance = tegra_emc_table[i].rate - rate;
  109. best = i;
  110. }
  111. }
  112. if (best < 0)
  113. return -EINVAL;
  114. pr_debug("%s: using %lu\n", __func__, tegra_emc_table[best].rate);
  115. return tegra_emc_table[best].rate * 2 * 1000;
  116. }
  117. /*
  118. * The EMC registers have shadow registers. When the EMC clock is updated
  119. * in the clock controller, the shadow registers are copied to the active
  120. * registers, allowing glitchless memory bus frequency changes.
  121. * This function updates the shadow registers for a new clock frequency,
  122. * and relies on the clock lock on the emc clock to avoid races between
  123. * multiple frequency changes
  124. */
  125. int tegra_emc_set_rate(unsigned long rate)
  126. {
  127. int i;
  128. int j;
  129. if (!tegra_emc_table)
  130. return -EINVAL;
  131. /*
  132. * The EMC clock rate is twice the bus rate, and the bus rate is
  133. * measured in kHz
  134. */
  135. rate = rate / 2 / 1000;
  136. for (i = 0; i < tegra_emc_table_size; i++)
  137. if (tegra_emc_table[i].rate == rate)
  138. break;
  139. if (i >= tegra_emc_table_size)
  140. return -EINVAL;
  141. pr_debug("%s: setting to %lu\n", __func__, rate);
  142. for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
  143. emc_writel(tegra_emc_table[i].regs[j], emc_reg_addr[j]);
  144. emc_readl(tegra_emc_table[i].regs[TEGRA_EMC_NUM_REGS - 1]);
  145. return 0;
  146. }
  147. void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
  148. {
  149. tegra_emc_table = table;
  150. tegra_emc_table_size = table_size;
  151. }