dma.c 5.5 KB

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  1. /* linux/arch/arm/mach-s3c2440/dma.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2440 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/sysdev.h>
  17. #include <linux/serial_core.h>
  18. #include <mach/map.h>
  19. #include <mach/dma.h>
  20. #include <plat/dma-s3c24xx.h>
  21. #include <plat/cpu.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-gpio.h>
  24. #include <plat/regs-ac97.h>
  25. #include <plat/regs-dma.h>
  26. #include <mach/regs-mem.h>
  27. #include <mach/regs-lcd.h>
  28. #include <mach/regs-sdi.h>
  29. #include <plat/regs-iis.h>
  30. #include <plat/regs-spi.h>
  31. static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
  32. [DMACH_XD0] = {
  33. .name = "xdreq0",
  34. .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  35. },
  36. [DMACH_XD1] = {
  37. .name = "xdreq1",
  38. .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  39. },
  40. [DMACH_SDI] = {
  41. .name = "sdi",
  42. .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  43. .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
  44. .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  45. .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  46. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  47. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  48. },
  49. [DMACH_SPI0] = {
  50. .name = "spi0",
  51. .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  52. .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
  53. .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
  54. },
  55. [DMACH_SPI1] = {
  56. .name = "spi1",
  57. .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  58. .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
  59. .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
  60. },
  61. [DMACH_UART0] = {
  62. .name = "uart0",
  63. .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  64. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  65. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  66. },
  67. [DMACH_UART1] = {
  68. .name = "uart1",
  69. .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  70. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  71. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  72. },
  73. [DMACH_UART2] = {
  74. .name = "uart2",
  75. .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  76. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  77. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  78. },
  79. [DMACH_TIMER] = {
  80. .name = "timer",
  81. .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  82. .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  83. .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  84. },
  85. [DMACH_I2S_IN] = {
  86. .name = "i2s-sdi",
  87. .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  88. .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  89. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  90. },
  91. [DMACH_I2S_OUT] = {
  92. .name = "i2s-sdo",
  93. .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
  94. .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  95. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  96. },
  97. [DMACH_PCM_IN] = {
  98. .name = "pcm-in",
  99. .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
  100. .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
  101. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  102. },
  103. [DMACH_PCM_OUT] = {
  104. .name = "pcm-out",
  105. .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
  106. .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
  107. .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  108. },
  109. [DMACH_MIC_IN] = {
  110. .name = "mic-in",
  111. .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
  112. .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
  113. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
  114. },
  115. [DMACH_USB_EP1] = {
  116. .name = "usb-ep1",
  117. .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
  118. },
  119. [DMACH_USB_EP2] = {
  120. .name = "usb-ep2",
  121. .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
  122. },
  123. [DMACH_USB_EP3] = {
  124. .name = "usb-ep3",
  125. .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
  126. },
  127. [DMACH_USB_EP4] = {
  128. .name = "usb-ep4",
  129. .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
  130. },
  131. };
  132. static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
  133. struct s3c24xx_dma_map *map)
  134. {
  135. chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
  136. }
  137. static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
  138. .select = s3c2440_dma_select,
  139. .dcon_mask = 7 << 24,
  140. .map = s3c2440_dma_mappings,
  141. .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
  142. };
  143. static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
  144. .channels = {
  145. [DMACH_SDI] = {
  146. .list = {
  147. [0] = 3 | DMA_CH_VALID,
  148. [1] = 2 | DMA_CH_VALID,
  149. [2] = 1 | DMA_CH_VALID,
  150. [3] = 0 | DMA_CH_VALID,
  151. },
  152. },
  153. [DMACH_I2S_IN] = {
  154. .list = {
  155. [0] = 1 | DMA_CH_VALID,
  156. [1] = 2 | DMA_CH_VALID,
  157. },
  158. },
  159. [DMACH_I2S_OUT] = {
  160. .list = {
  161. [0] = 2 | DMA_CH_VALID,
  162. [1] = 1 | DMA_CH_VALID,
  163. },
  164. },
  165. [DMACH_PCM_IN] = {
  166. .list = {
  167. [0] = 2 | DMA_CH_VALID,
  168. [1] = 1 | DMA_CH_VALID,
  169. },
  170. },
  171. [DMACH_PCM_OUT] = {
  172. .list = {
  173. [0] = 1 | DMA_CH_VALID,
  174. [1] = 3 | DMA_CH_VALID,
  175. },
  176. },
  177. [DMACH_MIC_IN] = {
  178. .list = {
  179. [0] = 3 | DMA_CH_VALID,
  180. [1] = 2 | DMA_CH_VALID,
  181. },
  182. },
  183. },
  184. };
  185. static int __init s3c2440_dma_add(struct sys_device *sysdev)
  186. {
  187. s3c2410_dma_init();
  188. s3c24xx_dma_order_set(&s3c2440_dma_order);
  189. return s3c24xx_dma_init_map(&s3c2440_dma_sel);
  190. }
  191. static struct sysdev_driver s3c2440_dma_driver = {
  192. .add = s3c2440_dma_add,
  193. };
  194. static int __init s3c2440_dma_init(void)
  195. {
  196. return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver);
  197. }
  198. arch_initcall(s3c2440_dma_init);