cm-x255.c 4.8 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/cm-x255.c
  3. *
  4. * Copyright (C) 2007, 2008 CompuLab, Ltd.
  5. * Mike Rapoport <mike@compulab.co.il>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/platform_device.h>
  12. #include <linux/irq.h>
  13. #include <linux/gpio.h>
  14. #include <linux/mtd/partitions.h>
  15. #include <linux/mtd/physmap.h>
  16. #include <linux/mtd/nand-gpio.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/spi/pxa2xx_spi.h>
  19. #include <asm/mach/arch.h>
  20. #include <asm/mach-types.h>
  21. #include <asm/mach/map.h>
  22. #include <mach/pxa25x.h>
  23. #include "generic.h"
  24. #define GPIO_NAND_CS (5)
  25. #define GPIO_NAND_ALE (4)
  26. #define GPIO_NAND_CLE (3)
  27. #define GPIO_NAND_RB (10)
  28. static unsigned long cmx255_pin_config[] = {
  29. /* AC'97 */
  30. GPIO28_AC97_BITCLK,
  31. GPIO29_AC97_SDATA_IN_0,
  32. GPIO30_AC97_SDATA_OUT,
  33. GPIO31_AC97_SYNC,
  34. /* BTUART */
  35. GPIO42_BTUART_RXD,
  36. GPIO43_BTUART_TXD,
  37. GPIO44_BTUART_CTS,
  38. GPIO45_BTUART_RTS,
  39. /* STUART */
  40. GPIO46_STUART_RXD,
  41. GPIO47_STUART_TXD,
  42. /* LCD */
  43. GPIOxx_LCD_TFT_16BPP,
  44. /* SSP1 */
  45. GPIO23_SSP1_SCLK,
  46. GPIO24_SSP1_SFRM,
  47. GPIO25_SSP1_TXD,
  48. GPIO26_SSP1_RXD,
  49. /* SSP2 */
  50. GPIO81_SSP2_CLK_OUT,
  51. GPIO82_SSP2_FRM_OUT,
  52. GPIO83_SSP2_TXD,
  53. GPIO84_SSP2_RXD,
  54. /* PC Card */
  55. GPIO48_nPOE,
  56. GPIO49_nPWE,
  57. GPIO50_nPIOR,
  58. GPIO51_nPIOW,
  59. GPIO52_nPCE_1,
  60. GPIO53_nPCE_2,
  61. GPIO54_nPSKTSEL,
  62. GPIO55_nPREG,
  63. GPIO56_nPWAIT,
  64. GPIO57_nIOIS16,
  65. /* SDRAM and local bus */
  66. GPIO15_nCS_1,
  67. GPIO78_nCS_2,
  68. GPIO79_nCS_3,
  69. GPIO80_nCS_4,
  70. GPIO33_nCS_5,
  71. GPIO18_RDY,
  72. /* GPIO */
  73. GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
  74. GPIO9_GPIO, /* PC card reset */
  75. /* NAND controls */
  76. GPIO5_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
  77. GPIO4_GPIO | MFP_LPM_DRIVE_LOW, /* NAND ALE */
  78. GPIO3_GPIO | MFP_LPM_DRIVE_LOW, /* NAND CLE */
  79. GPIO10_GPIO, /* NAND Ready/Busy */
  80. /* interrupts */
  81. GPIO22_GPIO, /* DM9000 interrupt */
  82. };
  83. #if defined(CONFIG_SPI_PXA2XX)
  84. static struct pxa2xx_spi_master pxa_ssp_master_info = {
  85. .num_chipselect = 1,
  86. };
  87. static struct spi_board_info spi_board_info[] __initdata = {
  88. [0] = {
  89. .modalias = "rtc-max6902",
  90. .max_speed_hz = 1000000,
  91. .bus_num = 1,
  92. .chip_select = 0,
  93. },
  94. };
  95. static void __init cmx255_init_rtc(void)
  96. {
  97. pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
  98. spi_register_board_info(ARRAY_AND_SIZE(spi_board_info));
  99. }
  100. #else
  101. static inline void cmx255_init_rtc(void) {}
  102. #endif
  103. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  104. static struct mtd_partition cmx255_nor_partitions[] = {
  105. {
  106. .name = "ARMmon",
  107. .size = 0x00030000,
  108. .offset = 0,
  109. .mask_flags = MTD_WRITEABLE /* force read-only */
  110. } , {
  111. .name = "ARMmon setup block",
  112. .size = 0x00010000,
  113. .offset = MTDPART_OFS_APPEND,
  114. .mask_flags = MTD_WRITEABLE /* force read-only */
  115. } , {
  116. .name = "kernel",
  117. .size = 0x00160000,
  118. .offset = MTDPART_OFS_APPEND,
  119. } , {
  120. .name = "ramdisk",
  121. .size = MTDPART_SIZ_FULL,
  122. .offset = MTDPART_OFS_APPEND
  123. }
  124. };
  125. static struct physmap_flash_data cmx255_nor_flash_data[] = {
  126. {
  127. .width = 2, /* bankwidth in bytes */
  128. .parts = cmx255_nor_partitions,
  129. .nr_parts = ARRAY_SIZE(cmx255_nor_partitions)
  130. }
  131. };
  132. static struct resource cmx255_nor_resource = {
  133. .start = PXA_CS0_PHYS,
  134. .end = PXA_CS0_PHYS + SZ_8M - 1,
  135. .flags = IORESOURCE_MEM,
  136. };
  137. static struct platform_device cmx255_nor = {
  138. .name = "physmap-flash",
  139. .id = -1,
  140. .dev = {
  141. .platform_data = cmx255_nor_flash_data,
  142. },
  143. .resource = &cmx255_nor_resource,
  144. .num_resources = 1,
  145. };
  146. static void __init cmx255_init_nor(void)
  147. {
  148. platform_device_register(&cmx255_nor);
  149. }
  150. #else
  151. static inline void cmx255_init_nor(void) {}
  152. #endif
  153. #if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
  154. static struct resource cmx255_nand_resource[] = {
  155. [0] = {
  156. .start = PXA_CS1_PHYS,
  157. .end = PXA_CS1_PHYS + 11,
  158. .flags = IORESOURCE_MEM,
  159. },
  160. [1] = {
  161. .start = PXA_CS5_PHYS,
  162. .end = PXA_CS5_PHYS + 3,
  163. .flags = IORESOURCE_MEM,
  164. },
  165. };
  166. static struct mtd_partition cmx255_nand_parts[] = {
  167. [0] = {
  168. .name = "cmx255-nand",
  169. .size = MTDPART_SIZ_FULL,
  170. .offset = 0,
  171. },
  172. };
  173. static struct gpio_nand_platdata cmx255_nand_platdata = {
  174. .gpio_nce = GPIO_NAND_CS,
  175. .gpio_cle = GPIO_NAND_CLE,
  176. .gpio_ale = GPIO_NAND_ALE,
  177. .gpio_rdy = GPIO_NAND_RB,
  178. .gpio_nwp = -1,
  179. .parts = cmx255_nand_parts,
  180. .num_parts = ARRAY_SIZE(cmx255_nand_parts),
  181. .chip_delay = 25,
  182. };
  183. static struct platform_device cmx255_nand = {
  184. .name = "gpio-nand",
  185. .num_resources = ARRAY_SIZE(cmx255_nand_resource),
  186. .resource = cmx255_nand_resource,
  187. .id = -1,
  188. .dev = {
  189. .platform_data = &cmx255_nand_platdata,
  190. }
  191. };
  192. static void __init cmx255_init_nand(void)
  193. {
  194. platform_device_register(&cmx255_nand);
  195. }
  196. #else
  197. static inline void cmx255_init_nand(void) {}
  198. #endif
  199. void __init cmx255_init(void)
  200. {
  201. pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config));
  202. cmx255_init_rtc();
  203. cmx255_init_nor();
  204. cmx255_init_nand();
  205. }