crt0.S 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113
  1. // (C) 2023 Victor Suarez Rovere <suarezvictor@gmail.com>
  2. // SPDX-License-Identifier: BSD-2-Clause
  3. //
  4. // (C) Litex and Misoc developers
  5. // see LITEX_CONTRIBUTORS file for additional authors
  6. //the fastcode_init code could be implemented in the main.c file
  7. .global main
  8. .global isr_handler
  9. .global _start
  10. _start:
  11. j crt_init
  12. nop
  13. nop
  14. nop
  15. nop
  16. nop
  17. nop
  18. nop
  19. .global trap_entry
  20. trap_entry:
  21. sw x1, - 1*4(sp)
  22. sw x5, - 2*4(sp)
  23. sw x6, - 3*4(sp)
  24. sw x7, - 4*4(sp)
  25. sw x10, - 5*4(sp)
  26. sw x11, - 6*4(sp)
  27. sw x12, - 7*4(sp)
  28. sw x13, - 8*4(sp)
  29. sw x14, - 9*4(sp)
  30. sw x15, -10*4(sp)
  31. sw x16, -11*4(sp)
  32. sw x17, -12*4(sp)
  33. sw x28, -13*4(sp)
  34. sw x29, -14*4(sp)
  35. sw x30, -15*4(sp)
  36. sw x31, -16*4(sp)
  37. addi sp,sp,-16*4
  38. call isr_handler
  39. lw x1 , 15*4(sp)
  40. lw x5, 14*4(sp)
  41. lw x6, 13*4(sp)
  42. lw x7, 12*4(sp)
  43. lw x10, 11*4(sp)
  44. lw x11, 10*4(sp)
  45. lw x12, 9*4(sp)
  46. lw x13, 8*4(sp)
  47. lw x14, 7*4(sp)
  48. lw x15, 6*4(sp)
  49. lw x16, 5*4(sp)
  50. lw x17, 4*4(sp)
  51. lw x28, 3*4(sp)
  52. lw x29, 2*4(sp)
  53. lw x30, 1*4(sp)
  54. lw x31, 0*4(sp)
  55. addi sp,sp,16*4
  56. mret
  57. .text
  58. crt_init:
  59. la sp, _fstack
  60. la a0, trap_entry
  61. csrw mtvec, a0
  62. data_init:
  63. la a0, _fast_data
  64. la a1, _efast_data
  65. la a2, _fast_data_loadaddr
  66. data_loop:
  67. beq a0,a1,data_done
  68. lw a3,0(a2)
  69. sw a3,0(a0)
  70. add a0,a0,4
  71. add a2,a2,4
  72. j data_loop
  73. data_done:
  74. bss_init:
  75. la a0, _fbss
  76. la a1, _ebss
  77. bss_loop:
  78. beq a0,a1,bss_done
  79. sw zero,0(a0)
  80. add a0,a0,4
  81. j bss_loop
  82. bss_done:
  83. fastcode_init:
  84. la a0, _fast_text
  85. la a1, _efast_text
  86. la a2, _fast_text_loadaddr
  87. fastcode_loop:
  88. beq a0,a1,fastcode_done
  89. lw a3,0(a2)
  90. sw a3,0(a0)
  91. add a0,a0,4
  92. add a2,a2,4
  93. j fastcode_loop
  94. fastcode_done:
  95. li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
  96. csrw mie,a0
  97. call main
  98. infinit_loop:
  99. j infinit_loop