hwsw_ws2023_gettoknow/vhdl/top/top.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
	--if you want to add further inputs/outputs, use the input/output
	-- names already defined in the pin planner
	port (
		clk    : in std_logic;
		
		keys : in std_logic_vector(3 downto 0);
		ledg : out std_logic_vector(8 downto 0);
		ledr : out std_logic_vector(17 downto 0)
	);
end entity;

architecture arch of top is

	component gettoknow is
	port (
		clk_clk       : in std_logic := '0'; -- clk
		reset_reset_n : in std_logic := '1'  -- reset_n
	);
	end component gettoknow;

	signal reset_n : std_logic;

begin
	u0 : component gettoknow
	port map (
		clk_clk       => clk,     --   clk.clk
		reset_reset_n => reset_n  -- reset.reset_n
	);
	
	-- use key(0) as reset for the Platform Desginer system
	reset_n <= keys(0);
	ledg <= (others=>'0');
	ledr <= (others=>'0');
end architecture;