ddca-ss2021/ca/miriv/quartus/miriv.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Intel and sold by Intel or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition
# Date created = 16:59:33  May 01, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		miriv_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:59:33  MAY 01, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_FILE ../vhdl/alu.vhd
set_global_assignment -name VHDL_FILE ../vhdl/wb.vhd
set_global_assignment -name VHDL_FILE ../vhdl/mem_pkg.vhd
set_global_assignment -name VHDL_FILE ../vhdl/core_pkg.vhd
set_global_assignment -name VHDL_FILE ../vhdl/regfile.vhd
set_global_assignment -name VHDL_FILE ../vhdl/op_pkg.vhd
set_global_assignment -name VHDL_FILE ../vhdl/memu.vhd
set_global_assignment -name VHDL_FILE ../vhdl/mem.vhd
set_global_assignment -name VHDL_FILE ../vhdl/fwd.vhd
set_global_assignment -name VHDL_FILE ../vhdl/fetch.vhd
set_global_assignment -name VHDL_FILE ../vhdl/exec.vhd
set_global_assignment -name VHDL_FILE ../vhdl/decode.vhd
set_global_assignment -name VHDL_FILE ../vhdl/ctrl.vhd
set_global_assignment -name VHDL_FILE ../vhdl/pipeline.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/cache_pkg.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/ram/single_clock_rw_ram_pkg.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/ram/single_clock_rw_ram.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/repl.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/data_st_1w.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/data_st.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/mgmt_st_1w.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/mgmt_st.vhd
set_global_assignment -name VHDL_FILE ../vhdl/cache/cache.vhd
set_global_assignment -name VHDL_FILE ../vhdl/core.vhd
set_global_assignment -name VHDL_FILE pll_altera.vhd
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name SDC_FILE miriv.sdc
set_global_assignment -name QXP_FILE bootloader.qxp
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL


# PINOUT
set_location_assignment PIN_Y2 -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
set_location_assignment PIN_R24 -to res_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to res_n
set_location_assignment PIN_G9 -to tx
set_instance_assignment -name IO_STANDARD "2.5 V" -to tx
set_location_assignment PIN_G12 -to rx
set_instance_assignment -name IO_STANDARD "2.5 V" -to rx








set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top