ddca-ss2021/ca/miriv/test/fetch/tb/tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;

library std; -- for Printing
use std.textio.all;

use work.mem_pkg.all;
use work.op_pkg.all;
use work.core_pkg.all;
use work.tb_util_pkg.all;

entity tb is
end entity;

architecture bench of tb is
	constant CLK_PERIOD : time := 10 ns;

	signal clk : std_logic;
	signal res_n : std_logic := '0';
	signal stop : boolean := false;
	
	file input_file : text;
	file output_ref_file : text;

	subtype addr is std_logic_vector(REG_BITS-1 downto 0);
	subtype data is std_logic_vector(DATA_WIDTH-1 downto 0);
	
	type data_arr is array(0 to 400) of MEM_DATA_TYPE;

	type input_t is
	record
		stall     	: std_logic;
		flush		: std_logic;
		pc_src		: std_logic;
		pc_in		: PC_TYPE;
	end record;

	type output_t is
	record
		pc_out 	: PC_TYPE;
		instr	: INSTR_TYPE;
	end record;

	signal inp  : input_t := (
		'0',
		'0',
		'0',
		(others => '0')
	);
	signal outp : output_t;
	signal mem : data_arr;
	signal mem_busy : std_logic;
	signal memout : MEM_OUT_TYPE;
	signal memin : MEM_IN_TYPE := (busy => '0', others => (others =>'0'));

	impure function read_next_input(file f : text) return input_t is
		variable l : line;
		variable result : input_t;
	begin
		l := get_next_valid_line(f);
		l := get_next_valid_line(f);
		result.stall := str_to_sl(l(1));

		l := get_next_valid_line(f);
		result.flush := str_to_sl(l(1));

		l := get_next_valid_line(f);
		result.pc_src := str_to_sl(l(1));

		l := get_next_valid_line(f);
		result.pc_in := bin_to_slv(l.all, PC_TYPE'LENGTH);

		return result;
	end function;

	impure function read_next_output(file f : text) return output_t is
		variable l : line;
		variable result : output_t;
	begin
		l := get_next_valid_line(f);
		l := get_next_valid_line(f);
		result.pc_out := bin_to_slv(l.all, PC_TYPE'LENGTH);

		l := get_next_valid_line(f);
		result.instr := bin_to_slv(l.all, INSTR_TYPE'LENGTH);
		return result;
	end function;

	procedure check_output(output_ref : output_t) is
		variable passed : boolean;
	begin
		passed := (outp = output_ref);

		if passed then
			report " PASSED: "
			& "stall="     & to_string(inp.stall)
			& " flush="  & to_string(inp.flush)
			& " pc_src="  & to_string(inp.pc_src)
			& " pc_in="   & to_string(inp.pc_in)
			severity note;
		else
			report "FAILED: "
			& "stall="     & to_string(inp.stall)
			& " flush="  & to_string(inp.flush)
			& " pc_src="  & to_string(inp.pc_src)
			& " pc_in="   & to_string(inp.pc_in) & lf
			& "**     expected: pc_out=" & to_string(output_ref.pc_out) & " instr=" & to_string(output_ref.instr) & lf
			& "**     actual:   pc_out=" & to_string(outp.pc_out)       & " instr=" & to_string(outp.instr) & lf
			severity error;
		end if;
	end procedure;

begin

	fetch_inst : entity work.fetch
	port map (
		clk     	=> clk,
		res_n   	=> res_n,
		stall   	=> inp.stall,
		flush		=> inp.flush,
		mem_busy	=> mem_busy,
		pcsrc		=> inp.pc_src,
		
		pc_in		=> inp.pc_in,	
		pc_out		=> outp.pc_out,
		instr		=> outp.instr,
		mem_out		=> memout,
		mem_in		=> memin
	);



	memcntrl : process(clk)
	begin
		if rising_edge(clk) then
			memin.rddata <= mem(to_integer(unsigned(memout.address)));
		end if;
	end process;

			
	stimulus : process
		variable fstatus: file_open_status;
	begin
		for i in 0 to 100 loop
			mem(i) <= std_logic_vector(to_unsigned(i, instr_type'LENGTH));
		end loop;
		res_n <= '0';
		wait until rising_edge(clk);
		res_n <= '1';
		
		file_open(fstatus, input_file, "testdata/input.txt", READ_MODE);
		
		

		while not endfile(input_file) loop
			inp <= read_next_input(input_file);
			timeout(1, CLK_PERIOD);
		end loop;
		
		wait;
	end process;

	output_checker : process
		variable fstatus: file_open_status;
		variable output_ref : output_t;
	begin
		file_open(fstatus, output_ref_file, "testdata/output.txt", READ_MODE);

		wait until res_n = '1';

		while not endfile(output_ref_file) loop
			output_ref := read_next_output(output_ref_file);

			wait until falling_edge(clk);
			check_output(output_ref);
			wait until rising_edge(clk);
		end loop;
		stop <= true;
		
		wait;
	end process;

	generate_clk : process
	begin
		clk_generate(clk, CLK_PERIOD, stop);
		wait;
	end process;

end architecture;