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ddca-ss2021
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report_wave.do

report_wave.do 11 KB
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  1. onerror {resume}
    2. 

  2. quietly WaveActivateNextPane {} 0
    3. 

  3. add wave -noupdate /tb_cpu/dut/pipeline_inst/clk
    4. 

  4. add wave -noupdate /tb_cpu/dut/pipeline_inst/res_n
    5. 

  5. add wave -noupdate -divider -height 40 fetch
    6. 

  6. add wave -noupdate -group fetch /tb_cpu/dut/pipeline_inst/fetch_inst/stall
    7. 

  7. add wave -noupdate -group fetch /tb_cpu/dut/pipeline_inst/fetch_inst/flush
    8. 

  8. add wave -noupdate -group fetch -radix hexadecimal /tb_cpu/dut/pipeline_inst/fetch_inst/pc_in
    9. 

  9. add wave -noupdate -group fetch /tb_cpu/dut/pipeline_inst/fetch_inst/pcsrc
    10. 

  10. add wave -noupdate -group fetch -radix hexadecimal /tb_cpu/dut/pipeline_inst/fetch_inst/instr
    11. 

  11. add wave -noupdate -group fetch -radix hexadecimal /tb_cpu/dut/pipeline_inst/fetch_inst/pc_out
    12. 

  12. add wave -noupdate -divider -height 40 decode
    13. 

  13. add wave -noupdate -group decode /tb_cpu/dut/pipeline_inst/decode_inst/stall
    14. 

  14. add wave -noupdate -group decode /tb_cpu/dut/pipeline_inst/decode_inst/flush
    15. 

  15. add wave -noupdate -group decode -radix hexadecimal /tb_cpu/dut/pipeline_inst/decode_inst/instr
    16. 

  16. add wave -noupdate -group decode -radix hexadecimal /tb_cpu/dut/pipeline_inst/decode_inst/pc_in
    17. 

  17. add wave -noupdate -group decode -radix hexadecimal /tb_cpu/dut/pipeline_inst/decode_inst/pc_out
    18. 

  18. add wave -position insertpoint  \
    19. 

  19. sim:/tb_cpu/dut/pipeline_inst/decode_inst/regfile_inst/wraddr \
    20. 

  20. sim:/tb_cpu/dut/pipeline_inst/decode_inst/regfile_inst/wrdata \
    21. 

  21. sim:/tb_cpu/dut/pipeline_inst/decode_inst/regfile_inst/regwrite \
    22. 

  22. sim:/tb_cpu/dut/pipeline_inst/decode_inst/regfile_inst/reg(1) \
    23. 

  23. sim:/tb_cpu/dut/pipeline_inst/decode_inst/regfile_inst/reg(2) \
    24. 

  24. sim:/tb_cpu/dut/pipeline_inst/decode_inst/regfile_inst/reg(3)
    25. 

  25. add wave -noupdate -divider -height 40 exec
    26. 

  26. add wave -noupdate -group exec /tb_cpu/dut/pipeline_inst/execute_inst/stall
    27. 

  27. add wave -noupdate -group exec /tb_cpu/dut/pipeline_inst/execute_inst/flush
    28. 

  28. add wave -noupdate -group exec -childformat {{/tb_cpu/dut/pipeline_inst/execute_inst/op.rs1 -radix unsigned} {/tb_cpu/dut/pipeline_inst/execute_inst/op.rs2 -radix unsigned} {/tb_cpu/dut/pipeline_inst/execute_inst/op.readdata1 -radix hexadecimal} {/tb_cpu/dut/pipeline_inst/execute_inst/op.readdata2 -radix hexadecimal} {/tb_cpu/dut/pipeline_inst/execute_inst/op.imm -radix hexadecimal}} -expand -subitemconfig {/tb_cpu/dut/pipeline_inst/execute_inst/op.rs1 {-height 16 -radix unsigned} /tb_cpu/dut/pipeline_inst/execute_inst/op.rs2 {-height 16 -radix unsigned} /tb_cpu/dut/pipeline_inst/execute_inst/op.readdata1 {-height 16 -radix hexadecimal} /tb_cpu/dut/pipeline_inst/execute_inst/op.readdata2 {-height 16 -radix hexadecimal} /tb_cpu/dut/pipeline_inst/execute_inst/op.imm {-height 16 -radix hexadecimal}} /tb_cpu/dut/pipeline_inst/execute_inst/op
    29. 

  29. add wave -noupdate -group exec -radix hexadecimal /tb_cpu/dut/pipeline_inst/execute_inst/pc_in
    30. 

  30. add wave -noupdate -group exec -childformat {{/tb_cpu/dut/pipeline_inst/execute_inst/reg_write_mem.reg -radix unsigned} {/tb_cpu/dut/pipeline_inst/execute_inst/reg_write_mem.data -radix hexadecimal}} -expand -subitemconfig {/tb_cpu/dut/pipeline_inst/execute_inst/reg_write_mem.reg {-height 16 -radix unsigned} /tb_cpu/dut/pipeline_inst/execute_inst/reg_write_mem.data {-height 16 -radix hexadecimal}} /tb_cpu/dut/pipeline_inst/execute_inst/reg_write_mem
    31. 

  31. add wave -noupdate -group exec /tb_cpu/dut/pipeline_inst/execute_inst/reg_write_wr
    32. 

  32. add wave -noupdate -group exec -radix hexadecimal /tb_cpu/dut/pipeline_inst/execute_inst/pc_new_out
    33. 

  33. add wave -noupdate -group exec -radix hexadecimal /tb_cpu/dut/pipeline_inst/execute_inst/pc_old_out
    34. 

  34. add wave -noupdate -group exec -radix hexadecimal /tb_cpu/dut/pipeline_inst/execute_inst/aluresult
    35. 

  35. add wave -noupdate -group exec /tb_cpu/dut/pipeline_inst/execute_inst/zero
    36. 

  36. add wave -noupdate -group exec -radix hexadecimal /tb_cpu/dut/pipeline_inst/execute_inst/wrdata
    37. 

  37. add wave -noupdate -group exec /tb_cpu/dut/pipeline_inst/execute_inst/do_fwd_A
    38. 

  38. add wave -noupdate -group exec /tb_cpu/dut/pipeline_inst/execute_inst/do_fwd_B
    39. 

  39. add wave -noupdate -group exec -radix decimal /tb_cpu/dut/pipeline_inst/execute_inst/fwd_val_A
    40. 

  40. add wave -noupdate -group exec -radix decimal /tb_cpu/dut/pipeline_inst/execute_inst/fwd_val_B
    41. 

  41. add wave -noupdate -group exec -radix hexadecimal /tb_cpu/dut/pipeline_inst/execute_inst/internal
    42. 

  42. add wave -noupdate -divider -height 40 mem
    43. 

  43. add wave -noupdate -group mem /tb_cpu/dut/pipeline_inst/memory_inst/stall
    44. 

  44. add wave -noupdate -group mem /tb_cpu/dut/pipeline_inst/memory_inst/flush
    45. 

  45. add wave -noupdate -group mem /tb_cpu/dut/pipeline_inst/memory_inst/mem_op
    46. 

  46. add wave -noupdate -group mem /tb_cpu/dut/pipeline_inst/memory_inst/zero
    47. 

  47. add wave -noupdate -group mem -radix hexadecimal /tb_cpu/dut/pipeline_inst/memory_inst/wrdata
    48. 

  48. add wave -noupdate -group mem /tb_cpu/dut/pipeline_inst/memory_inst/mem_busy
    49. 

  49. add wave -noupdate -group mem -radix hexadecimal /tb_cpu/dut/pipeline_inst/memory_inst/memresult
    50. 

  50. add wave -noupdate -group mem -radix hexadecimal /tb_cpu/dut/pipeline_inst/memory_inst/pc_new_in
    51. 

  51. add wave -noupdate -group mem -radix hexadecimal /tb_cpu/dut/pipeline_inst/memory_inst/pc_new_out
    52. 

  52. add wave -noupdate -group mem -radix hexadecimal /tb_cpu/dut/pipeline_inst/memory_inst/pc_old_in
    53. 

  53. add wave -noupdate -group mem -radix hexadecimal /tb_cpu/dut/pipeline_inst/memory_inst/pc_old_out
    54. 

  54. add wave -noupdate -group mem /tb_cpu/dut/pipeline_inst/memory_inst/pcsrc
    55. 

  55. add wave -noupdate -group mem /tb_cpu/dut/pipeline_inst/memory_inst/reg_write
    56. 

  56. add wave -noupdate -group mem -childformat {{/tb_cpu/dut/pipeline_inst/memory_inst/mem_in.rddata -radix hexadecimal}} -expand -subitemconfig {/tb_cpu/dut/pipeline_inst/memory_inst/mem_in.rddata {-height 16 -radix hexadecimal}} /tb_cpu/dut/pipeline_inst/memory_inst/mem_in
    57. 

  57. add wave -noupdate -group mem -childformat {{/tb_cpu/dut/pipeline_inst/memory_inst/mem_out.address -radix hexadecimal} {/tb_cpu/dut/pipeline_inst/memory_inst/mem_out.wrdata -radix hexadecimal}} -expand -subitemconfig {/tb_cpu/dut/pipeline_inst/memory_inst/mem_out.address {-height 16 -radix hexadecimal} /tb_cpu/dut/pipeline_inst/memory_inst/mem_out.wrdata {-height 16 -radix hexadecimal}} /tb_cpu/dut/pipeline_inst/memory_inst/mem_out
    58. 

  58. add wave -noupdate -divider -height 40 wb
    59. 

  59. add wave -noupdate -group wb /tb_cpu/dut/pipeline_inst/writeback_inst/stall
    60. 

  60. add wave -noupdate -group wb /tb_cpu/dut/pipeline_inst/writeback_inst/flush
    61. 

  61. add wave -noupdate -group wb /tb_cpu/dut/pipeline_inst/writeback_inst/op
    62. 

  62. add wave -noupdate -group wb -radix hexadecimal /tb_cpu/dut/pipeline_inst/writeback_inst/aluresult
    63. 

  63. add wave -noupdate -group wb -radix hexadecimal /tb_cpu/dut/pipeline_inst/writeback_inst/memresult
    64. 

  64. add wave -noupdate -group wb -radix hexadecimal /tb_cpu/dut/pipeline_inst/writeback_inst/pc_old_in
    65. 

  65. add wave -noupdate -group wb -childformat {{/tb_cpu/dut/pipeline_inst/writeback_inst/reg_write.reg -radix unsigned} {/tb_cpu/dut/pipeline_inst/writeback_inst/reg_write.data -radix hexadecimal}} -expand -subitemconfig {/tb_cpu/dut/pipeline_inst/writeback_inst/reg_write.reg {-height 16 -radix unsigned} /tb_cpu/dut/pipeline_inst/writeback_inst/reg_write.data {-height 16 -radix hexadecimal}} /tb_cpu/dut/pipeline_inst/writeback_inst/reg_write
    66. 

  66. add wave -noupdate -divider -height 40 ctrl
    67. 

  67. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/stall 
    68. 

  68. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/stall_fetch 
    69. 

  69. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/stall_dec
    70. 

  70. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/stall_exec 
    71. 

  71. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/stall_mem 
    72. 

  72. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/stall_wb 
    73. 

  73. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/flush_fetch 
    74. 

  74. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/flush_dec 
    75. 

  75. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/flush_exec 
    76. 

  76. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/flush_mem 
    77. 

  77. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/flush_wb 
    78. 

  78. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/wb_op_exec 
    79. 

  79. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/exec_op_dec 
    80. 

  80. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/pcsrc_in 
    81. 

  81. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/pcsrc_out 
    82. 

  82. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/stall_fwd_ctrl 
    83. 

  83. add wave -noupdate -group ctrl /tb_cpu/dut/pipeline_inst/ctrl_inst/flush_branch_ctrl
    84. 

  84. add wave -noupdate -divider -height 40 cache
    85. 

  85. add wave -position insertpoint  \
    86. 

  86. sim:/tb_cpu/dut/cache_inst/SETS_LD \
    87. 

  87. sim:/tb_cpu/dut/cache_inst/WAYS_LD \
    88. 

  88. sim:/tb_cpu/dut/cache_inst/ADDR_MASK \
    89. 

  89. sim:/tb_cpu/dut/cache_inst/clk \
    90. 

  90. sim:/tb_cpu/dut/cache_inst/res_n \
    91. 

  91. sim:/tb_cpu/dut/cache_inst/mem_out_cpu \
    92. 

  92. sim:/tb_cpu/dut/cache_inst/mem_in_cpu \
    93. 

  93. sim:/tb_cpu/dut/cache_inst/mem_out_mem \
    94. 

  94. sim:/tb_cpu/dut/cache_inst/mem_in_mem \
    95. 

  95. sim:/tb_cpu/dut/cache_inst/data \
    96. 

  96. sim:/tb_cpu/dut/cache_inst/mgmt \
    97. 

  97. sim:/tb_cpu/dut/cache_inst/internal \
    98. 

  98. sim:/tb_cpu/dut/cache_inst/internal_next \
    99. 

  99. sim:/tb_cpu/dut/cache_inst/cpu_tag \
    100. 

  100. sim:/tb_cpu/dut/cache_inst/cpu_index \
    101. 

  101. sim:/tb_cpu/dut/cache_inst/INITIAL_INTERNAL
    102. 

  102. add wave -noupdate -divider -height 40 mgmt_st
    103. 

  103. add wave -position insertpoint  \
    104. 

  104. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/SETS_LD \
    105. 

  105. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/WAYS_LD \
    106. 

  106. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/clk \
    107. 

  107. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/res_n \
    108. 

  108. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/index \
    109. 

  109. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/wr \
    110. 

  110. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/rd \
    111. 

  111. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/valid_in \
    112. 

  112. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/dirty_in \
    113. 

  113. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/tag_in \
    114. 

  114. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/way_out \
    115. 

  115. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/valid_out \
    116. 

  116. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/dirty_out \
    117. 

  117. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/tag_out \
    118. 

  118. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/hit_out \
    119. 

  119. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/mgmt_info_in \
    120. 

  120. sim:/tb_cpu/dut/cache_inst/mgmt_st_inst/mgmt_info_out
    121. 

  121. add wave -noupdate -divider -height 40 data_st
    122. 

  122. add wave -position insertpoint  \
    123. 

  123. sim:/tb_cpu/dut/cache_inst/data_st_inst/SETS_LD \
    124. 

  124. sim:/tb_cpu/dut/cache_inst/data_st_inst/WAYS_LD \
    125. 

  125. sim:/tb_cpu/dut/cache_inst/data_st_inst/clk \
    126. 

  126. sim:/tb_cpu/dut/cache_inst/data_st_inst/we \
    127. 

  127. sim:/tb_cpu/dut/cache_inst/data_st_inst/rd \
    128. 

  128. sim:/tb_cpu/dut/cache_inst/data_st_inst/way \
    129. 

  129. sim:/tb_cpu/dut/cache_inst/data_st_inst/index \
    130. 

  130. sim:/tb_cpu/dut/cache_inst/data_st_inst/byteena \
    131. 

  131. sim:/tb_cpu/dut/cache_inst/data_st_inst/data_in \
    132. 

  132. sim:/tb_cpu/dut/cache_inst/data_st_inst/data_out
    133. 

  133. TreeUpdate [SetDefaultTree]
    134. 

  134. WaveRestoreCursors {{Cursor 1} {345000 ps} 0}
    135. 

  135. quietly wave cursor active 1
    136. 

  136. configure wave -namecolwidth 150
    137. 

  137. configure wave -valuecolwidth 227
    138. 

  138. configure wave -justifyvalue left
    139. 

  139. configure wave -signalnamewidth 1
    140. 

  140. configure wave -snapdistance 10
    141. 

  141. configure wave -datasetprefix 0
    142. 

  142. configure wave -rowmargin 4
    143. 

  143. configure wave -childrowmargin 2
    144. 

  144. configure wave -gridoffset 0
    145. 

  145. configure wave -gridperiod 1
    146. 

  146. configure wave -griddelta 40
    147. 

  147. configure wave -timeline 0
    148. 

  148. configure wave -timelineunits us
    149. 

  149. update
    150. 

  150. WaveRestoreZoom {0 ps} {1190509 ps}
    151. 

  151.