Commit History

Author SHA1 Message Date
  Jason Gunthorpe 340c0c53ea fpga zynq: Fix incorrect ISR state on bootup 8 years ago
  Jason Gunthorpe 80baf649c2 fpga zynq: Remove priv->dev 8 years ago
  Jason Gunthorpe 1930c28651 fpga zynq: Add missing \n to messages 8 years ago
  Alan Tull 1df2865f8d fpga-mgr: add fpga image information struct 8 years ago
  Moritz Fischer 28f98a12f7 fpga: zynq-fpga: Fix issue with drvdata being overwritten. 9 years ago
  Moritz Fischer 4d10eaff5b fpga: zynq-fpga: Change fw format to handle bin instead of bit. 9 years ago
  Moritz Fischer 6376931bab fpga: zynq-fpga: Fix unbalanced clock handling 9 years ago
  Moritz Fischer 37784706bf fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000 9 years ago