wbsio_spi.c 6.0 KB

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  1. /*
  2. * This file is part of the flashrom project.
  3. *
  4. * Copyright (C) 2008 Peter Stuge <peter@stuge.se>
  5. * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #if defined(__i386__) || defined(__x86_64__)
  21. #include "flash.h"
  22. #include "chipdrivers.h"
  23. #include "programmer.h"
  24. #include "spi.h"
  25. #define WBSIO_PORT1 0x2e
  26. #define WBSIO_PORT2 0x4e
  27. static uint16_t wbsio_spibase = 0;
  28. static uint16_t wbsio_get_spibase(uint16_t port)
  29. {
  30. uint8_t id;
  31. uint16_t flashport = 0;
  32. w836xx_ext_enter(port);
  33. id = sio_read(port, 0x20);
  34. if (id != 0xa0) {
  35. msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
  36. goto done;
  37. }
  38. if (0 == (sio_read(port, 0x24) & 2)) {
  39. msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
  40. goto done;
  41. }
  42. sio_write(port, 0x07, 0x06);
  43. if (0 == (sio_read(port, 0x30) & 1)) {
  44. msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
  45. goto done;
  46. }
  47. flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63);
  48. done:
  49. w836xx_ext_leave(port);
  50. return flashport;
  51. }
  52. static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
  53. const unsigned char *writearr, unsigned char *readarr);
  54. static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
  55. static const struct spi_programmer spi_programmer_wbsio = {
  56. .type = SPI_CONTROLLER_WBSIO,
  57. .max_data_read = MAX_DATA_UNSPECIFIED,
  58. .max_data_write = MAX_DATA_UNSPECIFIED,
  59. .command = wbsio_spi_send_command,
  60. .multicommand = default_spi_send_multicommand,
  61. .read = wbsio_spi_read,
  62. .write_256 = spi_chip_write_1,
  63. };
  64. int wbsio_check_for_spi(void)
  65. {
  66. if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1)))
  67. if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2)))
  68. return 1;
  69. msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
  70. msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
  71. "1024 kB!\n", __func__);
  72. max_rom_decode.spi = 1024 * 1024;
  73. register_spi_programmer(&spi_programmer_wbsio);
  74. return 0;
  75. }
  76. /* W83627DHG has 11 command modes:
  77. * 1=1 command only
  78. * 2=1 command+1 data write
  79. * 3=1 command+2 data read
  80. * 4=1 command+3 address
  81. * 5=1 command+3 address+1 data write
  82. * 6=1 command+3 address+4 data write
  83. * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read
  84. * 8=1 command+3 address+1 data read
  85. * 9=1 command+3 address+2 data read
  86. * a=1 command+3 address+3 data read
  87. * b=1 command+3 address+4 data read
  88. *
  89. * mode[7:4] holds the command mode
  90. * mode[3:0] holds SPI address bits [19:16]
  91. *
  92. * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\
  93. * Would one more byte of RAM in the chip (to get all 24 bits) really make
  94. * such a big difference?
  95. */
  96. static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
  97. const unsigned char *writearr, unsigned char *readarr)
  98. {
  99. int i;
  100. uint8_t mode = 0;
  101. msg_pspew("%s:", __func__);
  102. if (1 == writecnt && 0 == readcnt) {
  103. mode = 0x10;
  104. } else if (2 == writecnt && 0 == readcnt) {
  105. OUTB(writearr[1], wbsio_spibase + 4);
  106. msg_pspew(" data=0x%02x", writearr[1]);
  107. mode = 0x20;
  108. } else if (1 == writecnt && 2 == readcnt) {
  109. mode = 0x30;
  110. } else if (4 == writecnt && 0 == readcnt) {
  111. msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
  112. for (i = 2; i < writecnt; i++) {
  113. OUTB(writearr[i], wbsio_spibase + i);
  114. msg_pspew("%02x", writearr[i]);
  115. }
  116. mode = 0x40 | (writearr[1] & 0x0f);
  117. } else if (5 == writecnt && 0 == readcnt) {
  118. msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
  119. for (i = 2; i < 4; i++) {
  120. OUTB(writearr[i], wbsio_spibase + i);
  121. msg_pspew("%02x", writearr[i]);
  122. }
  123. OUTB(writearr[i], wbsio_spibase + i);
  124. msg_pspew(" data=0x%02x", writearr[i]);
  125. mode = 0x50 | (writearr[1] & 0x0f);
  126. } else if (8 == writecnt && 0 == readcnt) {
  127. msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
  128. for (i = 2; i < 4; i++) {
  129. OUTB(writearr[i], wbsio_spibase + i);
  130. msg_pspew("%02x", writearr[i]);
  131. }
  132. msg_pspew(" data=0x");
  133. for (; i < writecnt; i++) {
  134. OUTB(writearr[i], wbsio_spibase + i);
  135. msg_pspew("%02x", writearr[i]);
  136. }
  137. mode = 0x60 | (writearr[1] & 0x0f);
  138. } else if (5 == writecnt && 4 == readcnt) {
  139. /* XXX: TODO not supported by flashrom infrastructure!
  140. * This mode, 7, discards the fifth byte in writecnt,
  141. * but since we can not express that in flashrom, fail
  142. * the operation for now.
  143. */
  144. ;
  145. } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) {
  146. msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
  147. for (i = 2; i < writecnt; i++) {
  148. OUTB(writearr[i], wbsio_spibase + i);
  149. msg_pspew("%02x", writearr[i]);
  150. }
  151. mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f);
  152. }
  153. msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode);
  154. if (!mode) {
  155. msg_perr("%s: unsupported command type wr=%d rd=%d\n",
  156. __func__, writecnt, readcnt);
  157. /* Command type refers to the number of bytes read/written. */
  158. return SPI_INVALID_LENGTH;
  159. }
  160. OUTB(writearr[0], wbsio_spibase);
  161. OUTB(mode, wbsio_spibase + 1);
  162. programmer_delay(10);
  163. if (!readcnt)
  164. return 0;
  165. msg_pspew("%s: returning data =", __func__);
  166. for (i = 0; i < readcnt; i++) {
  167. readarr[i] = INB(wbsio_spibase + 4 + i);
  168. msg_pspew(" 0x%02x", readarr[i]);
  169. }
  170. msg_pspew("\n");
  171. return 0;
  172. }
  173. static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len)
  174. {
  175. return read_memmapped(flash, buf, start, len);
  176. }
  177. #endif