cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc

create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports -filter { NAME =~  "clk" && DIRECTION == "IN" }]

set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]

set_property PACKAGE_PIN W4 [get_ports {ssel[3]}]
set_property PACKAGE_PIN V4 [get_ports {ssel[2]}]
set_property PACKAGE_PIN U4 [get_ports {ssel[1]}]
set_property PACKAGE_PIN U2 [get_ports {ssel[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ssel[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ssel[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ssel[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ssel[0]}]

set_property PACKAGE_PIN V7 [get_ports {seg[7]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]



set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]