ofw_pcibus.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431
  1. /*-
  2. * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
  3. *
  4. * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
  5. * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
  6. * Copyright (c) 2000, BSDi
  7. * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org>
  8. * All rights reserved.
  9. *
  10. * Redistribution and use in source and binary forms, with or without
  11. * modification, are permitted provided that the following conditions
  12. * are met:
  13. * 1. Redistributions of source code must retain the above copyright
  14. * notice unmodified, this list of conditions, and the following
  15. * disclaimer.
  16. * 2. Redistributions in binary form must reproduce the above copyright
  17. * notice, this list of conditions and the following disclaimer in the
  18. * documentation and/or other materials provided with the distribution.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30. */
  31. #include <sys/cdefs.h>
  32. __FBSDID("$FreeBSD$");
  33. #include <sys/param.h>
  34. #include <sys/bus.h>
  35. #include <sys/kernel.h>
  36. #include <sys/libkern.h>
  37. #include <sys/module.h>
  38. #include <sys/pciio.h>
  39. #include <sys/smp.h>
  40. #include <dev/ofw/ofw_bus.h>
  41. #include <dev/ofw/ofw_bus_subr.h>
  42. #include <dev/ofw/ofw_pci.h>
  43. #include <dev/ofw/openfirm.h>
  44. #include <machine/bus.h>
  45. #include <machine/intr_machdep.h>
  46. #include <machine/resource.h>
  47. #include <dev/pci/pcireg.h>
  48. #include <dev/pci/pcivar.h>
  49. #include <dev/pci/pci_private.h>
  50. #include "ofw_pcibus.h"
  51. #include "pcib_if.h"
  52. #include "pci_if.h"
  53. typedef uint32_t ofw_pci_intr_t;
  54. /* Methods */
  55. static device_probe_t ofw_pcibus_probe;
  56. static device_attach_t ofw_pcibus_attach;
  57. static pci_alloc_devinfo_t ofw_pcibus_alloc_devinfo;
  58. static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
  59. static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
  60. static bus_child_deleted_t ofw_pcibus_child_deleted;
  61. static int ofw_pcibus_child_pnpinfo_str_method(device_t cbdev, device_t child,
  62. char *buf, size_t buflen);
  63. static void ofw_pcibus_enum_devtree(device_t dev, u_int domain, u_int busno);
  64. static void ofw_pcibus_enum_bus(device_t dev, u_int domain, u_int busno);
  65. static device_method_t ofw_pcibus_methods[] = {
  66. /* Device interface */
  67. DEVMETHOD(device_probe, ofw_pcibus_probe),
  68. DEVMETHOD(device_attach, ofw_pcibus_attach),
  69. /* Bus interface */
  70. DEVMETHOD(bus_child_deleted, ofw_pcibus_child_deleted),
  71. DEVMETHOD(bus_child_pnpinfo_str, ofw_pcibus_child_pnpinfo_str_method),
  72. DEVMETHOD(bus_rescan, bus_null_rescan),
  73. DEVMETHOD(bus_get_cpus, ofw_pcibus_get_cpus),
  74. DEVMETHOD(bus_get_domain, ofw_pcibus_get_domain),
  75. /* PCI interface */
  76. DEVMETHOD(pci_alloc_devinfo, ofw_pcibus_alloc_devinfo),
  77. DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
  78. /* ofw_bus interface */
  79. DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
  80. DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
  81. DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
  82. DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
  83. DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
  84. DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
  85. DEVMETHOD_END
  86. };
  87. static devclass_t pci_devclass;
  88. DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods,
  89. sizeof(struct pci_softc), pci_driver);
  90. EARLY_DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0,
  91. BUS_PASS_BUS);
  92. MODULE_VERSION(ofw_pcibus, 1);
  93. MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
  94. static int ofw_devices_only = 0;
  95. TUNABLE_INT("hw.pci.ofw_devices_only", &ofw_devices_only);
  96. static int
  97. ofw_pcibus_probe(device_t dev)
  98. {
  99. if (ofw_bus_get_node(dev) == -1)
  100. return (ENXIO);
  101. device_set_desc(dev, "OFW PCI bus");
  102. return (BUS_PROBE_DEFAULT);
  103. }
  104. static int
  105. ofw_pcibus_attach(device_t dev)
  106. {
  107. u_int busno, domain;
  108. int error;
  109. error = pci_attach_common(dev);
  110. if (error)
  111. return (error);
  112. domain = pcib_get_domain(dev);
  113. busno = pcib_get_bus(dev);
  114. /*
  115. * Attach those children represented in the device tree.
  116. */
  117. ofw_pcibus_enum_devtree(dev, domain, busno);
  118. /*
  119. * We now attach any laggard devices. FDT, for instance, allows
  120. * the device tree to enumerate only some PCI devices. Apple's
  121. * OF device tree on some Grackle-based hardware can also miss
  122. * functions on multi-function cards.
  123. */
  124. if (!ofw_devices_only)
  125. ofw_pcibus_enum_bus(dev, domain, busno);
  126. return (bus_generic_attach(dev));
  127. }
  128. struct pci_devinfo *
  129. ofw_pcibus_alloc_devinfo(device_t dev)
  130. {
  131. struct ofw_pcibus_devinfo *dinfo;
  132. dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_WAITOK | M_ZERO);
  133. return (&dinfo->opd_dinfo);
  134. }
  135. static void
  136. ofw_pcibus_enum_devtree(device_t dev, u_int domain, u_int busno)
  137. {
  138. device_t pcib;
  139. struct ofw_pci_register pcir;
  140. struct ofw_pcibus_devinfo *dinfo;
  141. phandle_t node, child;
  142. u_int func, slot;
  143. int intline;
  144. pcib = device_get_parent(dev);
  145. node = ofw_bus_get_node(dev);
  146. for (child = OF_child(node); child != 0; child = OF_peer(child)) {
  147. if (OF_getencprop(child, "reg", (pcell_t *)&pcir,
  148. sizeof(pcir)) == -1)
  149. continue;
  150. slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
  151. func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
  152. /* Some OFW device trees contain dupes. */
  153. if (pci_find_dbsf(domain, busno, slot, func) != NULL)
  154. continue;
  155. /*
  156. * The preset in the intline register is usually bogus. Reset
  157. * it such that the PCI code will reroute the interrupt if
  158. * needed.
  159. */
  160. intline = PCI_INVALID_IRQ;
  161. if (OF_getproplen(child, "interrupts") > 0)
  162. intline = 0;
  163. PCIB_WRITE_CONFIG(pcib, busno, slot, func, PCIR_INTLINE,
  164. intline, 1);
  165. /*
  166. * Now set up the PCI and OFW bus layer devinfo and add it
  167. * to the PCI bus.
  168. */
  169. dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, dev,
  170. domain, busno, slot, func);
  171. if (dinfo == NULL)
  172. continue;
  173. if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
  174. 0) {
  175. pci_freecfg((struct pci_devinfo *)dinfo);
  176. continue;
  177. }
  178. dinfo->opd_dma_tag = NULL;
  179. pci_add_child(dev, (struct pci_devinfo *)dinfo);
  180. /*
  181. * Some devices don't have an intpin set, but do have
  182. * interrupts. These are fully specified, and set in the
  183. * interrupts property, so add that value to the device's
  184. * resource list.
  185. */
  186. if (dinfo->opd_dinfo.cfg.intpin == 0)
  187. ofw_bus_intr_to_rl(dev, child,
  188. &dinfo->opd_dinfo.resources, NULL);
  189. }
  190. }
  191. /*
  192. * The following is an almost exact clone of pci_add_children(), with the
  193. * addition that it (a) will not add children that have already been added,
  194. * and (b) will set up the OFW devinfo to point to invalid values. This is
  195. * to handle non-enumerated PCI children as exist in FDT and on the second
  196. * function of the Rage 128 in my Blue & White G3.
  197. */
  198. static void
  199. ofw_pcibus_enum_bus(device_t dev, u_int domain, u_int busno)
  200. {
  201. device_t pcib;
  202. struct ofw_pcibus_devinfo *dinfo;
  203. int maxslots;
  204. int s, f, pcifunchigh;
  205. uint8_t hdrtype;
  206. pcib = device_get_parent(dev);
  207. maxslots = PCIB_MAXSLOTS(pcib);
  208. for (s = 0; s <= maxslots; s++) {
  209. pcifunchigh = 0;
  210. f = 0;
  211. DELAY(1);
  212. hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1);
  213. if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
  214. continue;
  215. if (hdrtype & PCIM_MFDEV)
  216. pcifunchigh = PCI_FUNCMAX;
  217. for (f = 0; f <= pcifunchigh; f++) {
  218. /* Filter devices we have already added */
  219. if (pci_find_dbsf(domain, busno, s, f) != NULL)
  220. continue;
  221. dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(
  222. pcib, dev, domain, busno, s, f);
  223. if (dinfo == NULL)
  224. continue;
  225. dinfo->opd_dma_tag = NULL;
  226. dinfo->opd_obdinfo.obd_node = -1;
  227. dinfo->opd_obdinfo.obd_name = NULL;
  228. dinfo->opd_obdinfo.obd_compat = NULL;
  229. dinfo->opd_obdinfo.obd_type = NULL;
  230. dinfo->opd_obdinfo.obd_model = NULL;
  231. /*
  232. * For non OFW-devices, don't believe 0
  233. * for an interrupt.
  234. */
  235. if (dinfo->opd_dinfo.cfg.intline == 0) {
  236. dinfo->opd_dinfo.cfg.intline = PCI_INVALID_IRQ;
  237. PCIB_WRITE_CONFIG(pcib, busno, s, f,
  238. PCIR_INTLINE, PCI_INVALID_IRQ, 1);
  239. }
  240. pci_add_child(dev, (struct pci_devinfo *)dinfo);
  241. }
  242. }
  243. }
  244. static void
  245. ofw_pcibus_child_deleted(device_t dev, device_t child)
  246. {
  247. struct ofw_pcibus_devinfo *dinfo;
  248. dinfo = device_get_ivars(child);
  249. ofw_bus_gen_destroy_devinfo(&dinfo->opd_obdinfo);
  250. pci_child_deleted(dev, child);
  251. }
  252. static int
  253. ofw_pcibus_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
  254. size_t buflen)
  255. {
  256. pci_child_pnpinfo_str_method(cbdev, child, buf, buflen);
  257. if (ofw_bus_get_node(child) != -1) {
  258. strlcat(buf, " ", buflen); /* Separate info */
  259. ofw_bus_gen_child_pnpinfo_str(cbdev, child, buf, buflen);
  260. }
  261. return (0);
  262. }
  263. static int
  264. ofw_pcibus_assign_interrupt(device_t dev, device_t child)
  265. {
  266. ofw_pci_intr_t intr[2];
  267. phandle_t node, iparent;
  268. int isz, icells;
  269. node = ofw_bus_get_node(child);
  270. if (node == -1) {
  271. /* Non-firmware enumerated child, use standard routing */
  272. intr[0] = pci_get_intpin(child);
  273. return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
  274. intr[0]));
  275. }
  276. /*
  277. * Try to determine the node's interrupt parent so we know which
  278. * PIC to use.
  279. */
  280. iparent = -1;
  281. if (OF_getencprop(node, "interrupt-parent", &iparent,
  282. sizeof(iparent)) < 0)
  283. iparent = -1;
  284. icells = 1;
  285. if (iparent != -1)
  286. OF_getencprop(OF_node_from_xref(iparent), "#interrupt-cells",
  287. &icells, sizeof(icells));
  288. /*
  289. * Any AAPL,interrupts property gets priority and is
  290. * fully specified (i.e. does not need routing)
  291. */
  292. isz = OF_getencprop(node, "AAPL,interrupts", intr, sizeof(intr));
  293. if (isz == sizeof(intr[0])*icells)
  294. return ((iparent == -1) ? intr[0] : ofw_bus_map_intr(dev,
  295. iparent, icells, intr));
  296. isz = OF_getencprop(node, "interrupts", intr, sizeof(intr));
  297. if (isz == sizeof(intr[0])*icells) {
  298. if (iparent != -1)
  299. intr[0] = ofw_bus_map_intr(dev, iparent, icells, intr);
  300. } else {
  301. /* No property: our best guess is the intpin. */
  302. intr[0] = pci_get_intpin(child);
  303. }
  304. /*
  305. * If we got intr from a property, it may or may not be an intpin.
  306. * For on-board devices, it frequently is not, and is completely out
  307. * of the valid intpin range. For PCI slots, it hopefully is,
  308. * otherwise we will have trouble interfacing with non-OFW buses
  309. * such as cardbus.
  310. * Since we cannot tell which it is without violating layering, we
  311. * will always use the route_interrupt method, and treat exceptions
  312. * on the level they become apparent.
  313. */
  314. return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr[0]));
  315. }
  316. static const struct ofw_bus_devinfo *
  317. ofw_pcibus_get_devinfo(device_t bus, device_t dev)
  318. {
  319. struct ofw_pcibus_devinfo *dinfo;
  320. dinfo = device_get_ivars(dev);
  321. return (&dinfo->opd_obdinfo);
  322. }
  323. int
  324. ofw_pcibus_get_cpus(device_t dev, device_t child, enum cpu_sets op, size_t setsize,
  325. cpuset_t *cpuset)
  326. {
  327. int d, error;
  328. d = platform_node_numa_domain(ofw_bus_get_node(dev));
  329. switch (op) {
  330. case LOCAL_CPUS:
  331. if (setsize != sizeof(cpuset_t))
  332. return (EINVAL);
  333. *cpuset = cpuset_domain[d];
  334. return (0);
  335. case INTR_CPUS:
  336. error = bus_generic_get_cpus(dev, child, op, setsize, cpuset);
  337. if (error != 0)
  338. return (error);
  339. if (setsize != sizeof(cpuset_t))
  340. return (EINVAL);
  341. CPU_AND(cpuset, &cpuset_domain[d]);
  342. return (0);
  343. default:
  344. return (bus_generic_get_cpus(dev, child, op, setsize, cpuset));
  345. }
  346. return (0);
  347. }
  348. /*
  349. * Fetch the NUMA domain for the given device 'dev'.
  350. *
  351. * If a device has a _PXM method, map that to a NUMA domain.
  352. * Otherwise, pass the request up to the parent.
  353. * If there's no matching domain or the domain cannot be
  354. * determined, return ENOENT.
  355. */
  356. int
  357. ofw_pcibus_get_domain(device_t dev, device_t child, int *domain)
  358. {
  359. *domain = platform_node_numa_domain(ofw_bus_get_node(child));
  360. return (0);
  361. }