fpu_add.c 7.3 KB

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  1. /* $NetBSD: fpu_add.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */
  2. /*-
  3. * SPDX-License-Identifier: BSD-3-Clause
  4. *
  5. * Copyright (c) 1992, 1993
  6. * The Regents of the University of California. All rights reserved.
  7. *
  8. * This software was developed by the Computer Systems Engineering group
  9. * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  10. * contributed to Berkeley.
  11. *
  12. * All advertising materials mentioning features or use of this software
  13. * must display the following acknowledgement:
  14. * This product includes software developed by the University of
  15. * California, Lawrence Berkeley Laboratory.
  16. *
  17. * Redistribution and use in source and binary forms, with or without
  18. * modification, are permitted provided that the following conditions
  19. * are met:
  20. * 1. Redistributions of source code must retain the above copyright
  21. * notice, this list of conditions and the following disclaimer.
  22. * 2. Redistributions in binary form must reproduce the above copyright
  23. * notice, this list of conditions and the following disclaimer in the
  24. * documentation and/or other materials provided with the distribution.
  25. * 3. Neither the name of the University nor the names of its contributors
  26. * may be used to endorse or promote products derived from this software
  27. * without specific prior written permission.
  28. *
  29. * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  30. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  31. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  32. * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  33. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  37. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  38. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  39. * SUCH DAMAGE.
  40. *
  41. * @(#)fpu_add.c 8.1 (Berkeley) 6/11/93
  42. */
  43. /*
  44. * Perform an FPU add (return x + y).
  45. *
  46. * To subtract, negate y and call add.
  47. */
  48. #include <sys/cdefs.h>
  49. __FBSDID("$FreeBSD$");
  50. #include <sys/types.h>
  51. #include <sys/systm.h>
  52. #include <machine/fpu.h>
  53. #include <machine/ieeefp.h>
  54. #include <machine/reg.h>
  55. #include <powerpc/fpu/fpu_arith.h>
  56. #include <powerpc/fpu/fpu_emu.h>
  57. struct fpn *
  58. fpu_add(struct fpemu *fe)
  59. {
  60. struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2, *r;
  61. u_int r0, r1, r2, r3;
  62. int rd;
  63. /*
  64. * Put the `heavier' operand on the right (see fpu_emu.h).
  65. * Then we will have one of the following cases, taken in the
  66. * following order:
  67. *
  68. * - y = NaN. Implied: if only one is a signalling NaN, y is.
  69. * The result is y.
  70. * - y = Inf. Implied: x != NaN (is 0, number, or Inf: the NaN
  71. * case was taken care of earlier).
  72. * If x = -y, the result is NaN. Otherwise the result
  73. * is y (an Inf of whichever sign).
  74. * - y is 0. Implied: x = 0.
  75. * If x and y differ in sign (one positive, one negative),
  76. * the result is +0 except when rounding to -Inf. If same:
  77. * +0 + +0 = +0; -0 + -0 = -0.
  78. * - x is 0. Implied: y != 0.
  79. * Result is y.
  80. * - other. Implied: both x and y are numbers.
  81. * Do addition a la Hennessey & Patterson.
  82. */
  83. DPRINTF(FPE_REG, ("fpu_add:\n"));
  84. DUMPFPN(FPE_REG, x);
  85. DUMPFPN(FPE_REG, y);
  86. DPRINTF(FPE_REG, ("=>\n"));
  87. ORDER(x, y);
  88. if (ISNAN(y)) {
  89. fe->fe_cx |= FPSCR_VXSNAN;
  90. DUMPFPN(FPE_REG, y);
  91. return (y);
  92. }
  93. if (ISINF(y)) {
  94. if (ISINF(x) && x->fp_sign != y->fp_sign) {
  95. fe->fe_cx |= FPSCR_VXISI;
  96. return (fpu_newnan(fe));
  97. }
  98. DUMPFPN(FPE_REG, y);
  99. return (y);
  100. }
  101. rd = ((fe->fe_fpscr) & FPSCR_RN);
  102. if (ISZERO(y)) {
  103. if (rd != FP_RM) /* only -0 + -0 gives -0 */
  104. y->fp_sign &= x->fp_sign;
  105. else /* any -0 operand gives -0 */
  106. y->fp_sign |= x->fp_sign;
  107. DUMPFPN(FPE_REG, y);
  108. return (y);
  109. }
  110. if (ISZERO(x)) {
  111. DUMPFPN(FPE_REG, y);
  112. return (y);
  113. }
  114. /*
  115. * We really have two numbers to add, although their signs may
  116. * differ. Make the exponents match, by shifting the smaller
  117. * number right (e.g., 1.011 => 0.1011) and increasing its
  118. * exponent (2^3 => 2^4). Note that we do not alter the exponents
  119. * of x and y here.
  120. */
  121. r = &fe->fe_f3;
  122. r->fp_class = FPC_NUM;
  123. if (x->fp_exp == y->fp_exp) {
  124. r->fp_exp = x->fp_exp;
  125. r->fp_sticky = 0;
  126. } else {
  127. if (x->fp_exp < y->fp_exp) {
  128. /*
  129. * Try to avoid subtract case iii (see below).
  130. * This also guarantees that x->fp_sticky = 0.
  131. */
  132. SWAP(x, y);
  133. }
  134. /* now x->fp_exp > y->fp_exp */
  135. r->fp_exp = x->fp_exp;
  136. r->fp_sticky = fpu_shr(y, x->fp_exp - y->fp_exp);
  137. }
  138. r->fp_sign = x->fp_sign;
  139. if (x->fp_sign == y->fp_sign) {
  140. FPU_DECL_CARRY
  141. /*
  142. * The signs match, so we simply add the numbers. The result
  143. * may be `supernormal' (as big as 1.111...1 + 1.111...1, or
  144. * 11.111...0). If so, a single bit shift-right will fix it
  145. * (but remember to adjust the exponent).
  146. */
  147. /* r->fp_mant = x->fp_mant + y->fp_mant */
  148. FPU_ADDS(r->fp_mant[3], x->fp_mant[3], y->fp_mant[3]);
  149. FPU_ADDCS(r->fp_mant[2], x->fp_mant[2], y->fp_mant[2]);
  150. FPU_ADDCS(r->fp_mant[1], x->fp_mant[1], y->fp_mant[1]);
  151. FPU_ADDC(r0, x->fp_mant[0], y->fp_mant[0]);
  152. if ((r->fp_mant[0] = r0) >= FP_2) {
  153. (void) fpu_shr(r, 1);
  154. r->fp_exp++;
  155. }
  156. } else {
  157. FPU_DECL_CARRY
  158. /*
  159. * The signs differ, so things are rather more difficult.
  160. * H&P would have us negate the negative operand and add;
  161. * this is the same as subtracting the negative operand.
  162. * This is quite a headache. Instead, we will subtract
  163. * y from x, regardless of whether y itself is the negative
  164. * operand. When this is done one of three conditions will
  165. * hold, depending on the magnitudes of x and y:
  166. * case i) |x| > |y|. The result is just x - y,
  167. * with x's sign, but it may need to be normalized.
  168. * case ii) |x| = |y|. The result is 0 (maybe -0)
  169. * so must be fixed up.
  170. * case iii) |x| < |y|. We goofed; the result should
  171. * be (y - x), with the same sign as y.
  172. * We could compare |x| and |y| here and avoid case iii,
  173. * but that would take just as much work as the subtract.
  174. * We can tell case iii has occurred by an overflow.
  175. *
  176. * N.B.: since x->fp_exp >= y->fp_exp, x->fp_sticky = 0.
  177. */
  178. /* r->fp_mant = x->fp_mant - y->fp_mant */
  179. FPU_SET_CARRY(y->fp_sticky);
  180. FPU_SUBCS(r3, x->fp_mant[3], y->fp_mant[3]);
  181. FPU_SUBCS(r2, x->fp_mant[2], y->fp_mant[2]);
  182. FPU_SUBCS(r1, x->fp_mant[1], y->fp_mant[1]);
  183. FPU_SUBC(r0, x->fp_mant[0], y->fp_mant[0]);
  184. if (r0 < FP_2) {
  185. /* cases i and ii */
  186. if ((r0 | r1 | r2 | r3) == 0) {
  187. /* case ii */
  188. r->fp_class = FPC_ZERO;
  189. r->fp_sign = rd == FP_RM;
  190. return (r);
  191. }
  192. } else {
  193. /*
  194. * Oops, case iii. This can only occur when the
  195. * exponents were equal, in which case neither
  196. * x nor y have sticky bits set. Flip the sign
  197. * (to y's sign) and negate the result to get y - x.
  198. */
  199. #ifdef DIAGNOSTIC
  200. if (x->fp_exp != y->fp_exp || r->fp_sticky)
  201. panic("fpu_add");
  202. #endif
  203. r->fp_sign = y->fp_sign;
  204. FPU_SUBS(r3, 0, r3);
  205. FPU_SUBCS(r2, 0, r2);
  206. FPU_SUBCS(r1, 0, r1);
  207. FPU_SUBC(r0, 0, r0);
  208. }
  209. r->fp_mant[3] = r3;
  210. r->fp_mant[2] = r2;
  211. r->fp_mant[1] = r1;
  212. r->fp_mant[0] = r0;
  213. if (r0 < FP_1)
  214. fpu_norm(r);
  215. }
  216. DUMPFPN(FPE_REG, r);
  217. return (r);
  218. }