zybo.dts 2.0 KB

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  1. /*-
  2. * Copyright (c) 2016 The FreeBSD Foundation
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions
  7. * are met:
  8. * 1. Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. *
  14. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17. * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24. * SUCH DAMAGE.
  25. *
  26. * $FreeBSD$
  27. */
  28. /dts-v1/;
  29. /include/ "zynq-7000.dtsi"
  30. / {
  31. model = "zybo";
  32. compatible = "digilent,zybo", "xlnx,zynq-7000";
  33. memory {
  34. // First megabyte isn't accessible by all interconnect masters.
  35. device_type = "memory";
  36. reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */
  37. };
  38. chosen {
  39. stdin = &uart1;
  40. stdout = &uart1;
  41. };
  42. };
  43. &slcr {
  44. clock-frequency = <50000000>; // 50Mhz PS_CLK
  45. };
  46. &global_timer {
  47. clock-frequency = <325000000>; // 325Mhz
  48. };
  49. &uart1 {
  50. status = "okay";
  51. };
  52. &eth0 {
  53. status = "okay";
  54. };
  55. &qspi0 {
  56. status = "okay";
  57. flash0 {
  58. compatible = "st,m25p", "s25fl128";
  59. spi-chipselect = <0>;
  60. };
  61. };
  62. &sdhci0 {
  63. status = "okay";
  64. };
  65. &ehci0 {
  66. status = "okay";
  67. };