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drivers
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s5p-cec
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regs-cec.h

regs-cec.h 2.8 KB
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  1. /* drivers/media/platform/s5p-cec/regs-cec.h
    2. 

  2.  *
    3. 

  3.  * Copyright (c) 2010 Samsung Electronics
    4. 

  4.  *		http://www.samsung.com/
    5. 

  5.  *
    6. 

  6.  *  register header file for Samsung TVOUT driver
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11.  */
    12. 

  12. 

  13. #ifndef __EXYNOS_REGS__H
    14. 

  14. #define __EXYNOS_REGS__H
    15. 

  15. 

  16. /*
    17. 

  17.  * Register part
    18. 

  18.  */
    19. 

  19. #define S5P_CEC_STATUS_0			(0x0000)
    20. 

  20. #define S5P_CEC_STATUS_1			(0x0004)
    21. 

  21. #define S5P_CEC_STATUS_2			(0x0008)
    22. 

  22. #define S5P_CEC_STATUS_3			(0x000C)
    23. 

  23. #define S5P_CEC_IRQ_MASK			(0x0010)
    24. 

  24. #define S5P_CEC_IRQ_CLEAR			(0x0014)
    25. 

  25. #define S5P_CEC_LOGIC_ADDR			(0x0020)
    26. 

  26. #define S5P_CEC_DIVISOR_0			(0x0030)
    27. 

  27. #define S5P_CEC_DIVISOR_1			(0x0034)
    28. 

  28. #define S5P_CEC_DIVISOR_2			(0x0038)
    29. 

  29. #define S5P_CEC_DIVISOR_3			(0x003C)
    30. 

  30. 

  31. #define S5P_CEC_TX_CTRL				(0x0040)
    32. 

  32. #define S5P_CEC_TX_BYTES			(0x0044)
    33. 

  33. #define S5P_CEC_TX_STAT0			(0x0060)
    34. 

  34. #define S5P_CEC_TX_STAT1			(0x0064)
    35. 

  35. #define S5P_CEC_TX_BUFF0			(0x0080)
    36. 

  36. #define S5P_CEC_TX_BUFF1			(0x0084)
    37. 

  37. #define S5P_CEC_TX_BUFF2			(0x0088)
    38. 

  38. #define S5P_CEC_TX_BUFF3			(0x008C)
    39. 

  39. #define S5P_CEC_TX_BUFF4			(0x0090)
    40. 

  40. #define S5P_CEC_TX_BUFF5			(0x0094)
    41. 

  41. #define S5P_CEC_TX_BUFF6			(0x0098)
    42. 

  42. #define S5P_CEC_TX_BUFF7			(0x009C)
    43. 

  43. #define S5P_CEC_TX_BUFF8			(0x00A0)
    44. 

  44. #define S5P_CEC_TX_BUFF9			(0x00A4)
    45. 

  45. #define S5P_CEC_TX_BUFF10			(0x00A8)
    46. 

  46. #define S5P_CEC_TX_BUFF11			(0x00AC)
    47. 

  47. #define S5P_CEC_TX_BUFF12			(0x00B0)
    48. 

  48. #define S5P_CEC_TX_BUFF13			(0x00B4)
    49. 

  49. #define S5P_CEC_TX_BUFF14			(0x00B8)
    50. 

  50. #define S5P_CEC_TX_BUFF15			(0x00BC)
    51. 

  51. 

  52. #define S5P_CEC_RX_CTRL				(0x00C0)
    53. 

  53. #define S5P_CEC_RX_STAT0			(0x00E0)
    54. 

  54. #define S5P_CEC_RX_STAT1			(0x00E4)
    55. 

  55. #define S5P_CEC_RX_BUFF0			(0x0100)
    56. 

  56. #define S5P_CEC_RX_BUFF1			(0x0104)
    57. 

  57. #define S5P_CEC_RX_BUFF2			(0x0108)
    58. 

  58. #define S5P_CEC_RX_BUFF3			(0x010C)
    59. 

  59. #define S5P_CEC_RX_BUFF4			(0x0110)
    60. 

  60. #define S5P_CEC_RX_BUFF5			(0x0114)
    61. 

  61. #define S5P_CEC_RX_BUFF6			(0x0118)
    62. 

  62. #define S5P_CEC_RX_BUFF7			(0x011C)
    63. 

  63. #define S5P_CEC_RX_BUFF8			(0x0120)
    64. 

  64. #define S5P_CEC_RX_BUFF9			(0x0124)
    65. 

  65. #define S5P_CEC_RX_BUFF10			(0x0128)
    66. 

  66. #define S5P_CEC_RX_BUFF11			(0x012C)
    67. 

  67. #define S5P_CEC_RX_BUFF12			(0x0130)
    68. 

  68. #define S5P_CEC_RX_BUFF13			(0x0134)
    69. 

  69. #define S5P_CEC_RX_BUFF14			(0x0138)
    70. 

  70. #define S5P_CEC_RX_BUFF15			(0x013C)
    71. 

  71. 

  72. #define S5P_CEC_RX_FILTER_CTRL			(0x0180)
    73. 

  73. #define S5P_CEC_RX_FILTER_TH			(0x0184)
    74. 

  74. 

  75. /*
    76. 

  76.  * Bit definition part
    77. 

  77.  */
    78. 

  78. #define S5P_CEC_IRQ_TX_DONE			(1<<0)
    79. 

  79. #define S5P_CEC_IRQ_TX_ERROR			(1<<1)
    80. 

  80. #define S5P_CEC_IRQ_RX_DONE			(1<<4)
    81. 

  81. #define S5P_CEC_IRQ_RX_ERROR			(1<<5)
    82. 

  82. 

  83. #define S5P_CEC_TX_CTRL_START			(1<<0)
    84. 

  84. #define S5P_CEC_TX_CTRL_BCAST			(1<<1)
    85. 

  85. #define S5P_CEC_TX_CTRL_RETRY			(0x04<<4)
    86. 

  86. #define S5P_CEC_TX_CTRL_RESET			(1<<7)
    87. 

  87. 

  88. #define S5P_CEC_RX_CTRL_ENABLE			(1<<0)
    89. 

  89. #define S5P_CEC_RX_CTRL_RESET			(1<<7)
    90. 

  90. 

  91. #define S5P_CEC_LOGIC_ADDR_MASK			(0xF)
    92. 

  92. 

  93. /* PMU Registers for PHY */
    94. 

  94. #define EXYNOS_HDMI_PHY_CONTROL			0x700
    95. 

  95. 

  96. #endif	/* __EXYNOS_REGS__H	*/
    97. 

  97.