cxgbit_main.c 17 KB

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  1. /*
  2. * Copyright (c) 2016 Chelsio Communications, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #define DRV_NAME "cxgbit"
  9. #define DRV_VERSION "1.0.0-ko"
  10. #define pr_fmt(fmt) DRV_NAME ": " fmt
  11. #include "cxgbit.h"
  12. #ifdef CONFIG_CHELSIO_T4_DCB
  13. #include <net/dcbevent.h>
  14. #include "cxgb4_dcb.h"
  15. #endif
  16. LIST_HEAD(cdev_list_head);
  17. /* cdev list lock */
  18. DEFINE_MUTEX(cdev_list_lock);
  19. void _cxgbit_free_cdev(struct kref *kref)
  20. {
  21. struct cxgbit_device *cdev;
  22. cdev = container_of(kref, struct cxgbit_device, kref);
  23. cxgbi_ppm_release(cdev2ppm(cdev));
  24. kfree(cdev);
  25. }
  26. static void cxgbit_set_mdsl(struct cxgbit_device *cdev)
  27. {
  28. struct cxgb4_lld_info *lldi = &cdev->lldi;
  29. u32 mdsl;
  30. #define ULP2_MAX_PKT_LEN 16224
  31. #define ISCSI_PDU_NONPAYLOAD_LEN 312
  32. mdsl = min_t(u32, lldi->iscsi_iolen - ISCSI_PDU_NONPAYLOAD_LEN,
  33. ULP2_MAX_PKT_LEN - ISCSI_PDU_NONPAYLOAD_LEN);
  34. mdsl = min_t(u32, mdsl, 8192);
  35. mdsl = min_t(u32, mdsl, (MAX_SKB_FRAGS - 1) * PAGE_SIZE);
  36. cdev->mdsl = mdsl;
  37. }
  38. static void *cxgbit_uld_add(const struct cxgb4_lld_info *lldi)
  39. {
  40. struct cxgbit_device *cdev;
  41. if (is_t4(lldi->adapter_type))
  42. return ERR_PTR(-ENODEV);
  43. cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
  44. if (!cdev)
  45. return ERR_PTR(-ENOMEM);
  46. kref_init(&cdev->kref);
  47. spin_lock_init(&cdev->np_lock);
  48. cdev->lldi = *lldi;
  49. cxgbit_set_mdsl(cdev);
  50. if (cxgbit_ddp_init(cdev) < 0) {
  51. kfree(cdev);
  52. return ERR_PTR(-EINVAL);
  53. }
  54. if (!test_bit(CDEV_DDP_ENABLE, &cdev->flags))
  55. pr_info("cdev %s ddp init failed\n",
  56. pci_name(lldi->pdev));
  57. if (lldi->fw_vers >= 0x10d2b00)
  58. set_bit(CDEV_ISO_ENABLE, &cdev->flags);
  59. spin_lock_init(&cdev->cskq.lock);
  60. INIT_LIST_HEAD(&cdev->cskq.list);
  61. mutex_lock(&cdev_list_lock);
  62. list_add_tail(&cdev->list, &cdev_list_head);
  63. mutex_unlock(&cdev_list_lock);
  64. pr_info("cdev %s added for iSCSI target transport\n",
  65. pci_name(lldi->pdev));
  66. return cdev;
  67. }
  68. static void cxgbit_close_conn(struct cxgbit_device *cdev)
  69. {
  70. struct cxgbit_sock *csk;
  71. struct sk_buff *skb;
  72. bool wakeup_thread = false;
  73. spin_lock_bh(&cdev->cskq.lock);
  74. list_for_each_entry(csk, &cdev->cskq.list, list) {
  75. skb = alloc_skb(0, GFP_ATOMIC);
  76. if (!skb)
  77. continue;
  78. spin_lock_bh(&csk->rxq.lock);
  79. __skb_queue_tail(&csk->rxq, skb);
  80. if (skb_queue_len(&csk->rxq) == 1)
  81. wakeup_thread = true;
  82. spin_unlock_bh(&csk->rxq.lock);
  83. if (wakeup_thread) {
  84. wake_up(&csk->waitq);
  85. wakeup_thread = false;
  86. }
  87. }
  88. spin_unlock_bh(&cdev->cskq.lock);
  89. }
  90. static void cxgbit_detach_cdev(struct cxgbit_device *cdev)
  91. {
  92. bool free_cdev = false;
  93. spin_lock_bh(&cdev->cskq.lock);
  94. if (list_empty(&cdev->cskq.list))
  95. free_cdev = true;
  96. spin_unlock_bh(&cdev->cskq.lock);
  97. if (free_cdev) {
  98. mutex_lock(&cdev_list_lock);
  99. list_del(&cdev->list);
  100. mutex_unlock(&cdev_list_lock);
  101. cxgbit_put_cdev(cdev);
  102. } else {
  103. cxgbit_close_conn(cdev);
  104. }
  105. }
  106. static int cxgbit_uld_state_change(void *handle, enum cxgb4_state state)
  107. {
  108. struct cxgbit_device *cdev = handle;
  109. switch (state) {
  110. case CXGB4_STATE_UP:
  111. set_bit(CDEV_STATE_UP, &cdev->flags);
  112. pr_info("cdev %s state UP.\n", pci_name(cdev->lldi.pdev));
  113. break;
  114. case CXGB4_STATE_START_RECOVERY:
  115. clear_bit(CDEV_STATE_UP, &cdev->flags);
  116. cxgbit_close_conn(cdev);
  117. pr_info("cdev %s state RECOVERY.\n", pci_name(cdev->lldi.pdev));
  118. break;
  119. case CXGB4_STATE_DOWN:
  120. pr_info("cdev %s state DOWN.\n", pci_name(cdev->lldi.pdev));
  121. break;
  122. case CXGB4_STATE_DETACH:
  123. clear_bit(CDEV_STATE_UP, &cdev->flags);
  124. pr_info("cdev %s state DETACH.\n", pci_name(cdev->lldi.pdev));
  125. cxgbit_detach_cdev(cdev);
  126. break;
  127. default:
  128. pr_info("cdev %s unknown state %d.\n",
  129. pci_name(cdev->lldi.pdev), state);
  130. break;
  131. }
  132. return 0;
  133. }
  134. static void
  135. cxgbit_process_ddpvld(struct cxgbit_sock *csk, struct cxgbit_lro_pdu_cb *pdu_cb,
  136. u32 ddpvld)
  137. {
  138. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_HCRC_SHIFT)) {
  139. pr_info("tid 0x%x, status 0x%x, hcrc bad.\n", csk->tid, ddpvld);
  140. pdu_cb->flags |= PDUCBF_RX_HCRC_ERR;
  141. }
  142. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_DCRC_SHIFT)) {
  143. pr_info("tid 0x%x, status 0x%x, dcrc bad.\n", csk->tid, ddpvld);
  144. pdu_cb->flags |= PDUCBF_RX_DCRC_ERR;
  145. }
  146. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_PAD_SHIFT))
  147. pr_info("tid 0x%x, status 0x%x, pad bad.\n", csk->tid, ddpvld);
  148. if ((ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_DDP_SHIFT)) &&
  149. (!(pdu_cb->flags & PDUCBF_RX_DATA))) {
  150. pdu_cb->flags |= PDUCBF_RX_DATA_DDPD;
  151. }
  152. }
  153. static void
  154. cxgbit_lro_add_packet_rsp(struct sk_buff *skb, u8 op, const __be64 *rsp)
  155. {
  156. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  157. struct cxgbit_lro_pdu_cb *pdu_cb = cxgbit_skb_lro_pdu_cb(skb,
  158. lro_cb->pdu_idx);
  159. struct cpl_rx_iscsi_ddp *cpl = (struct cpl_rx_iscsi_ddp *)(rsp + 1);
  160. cxgbit_process_ddpvld(lro_cb->csk, pdu_cb, be32_to_cpu(cpl->ddpvld));
  161. pdu_cb->flags |= PDUCBF_RX_STATUS;
  162. pdu_cb->ddigest = ntohl(cpl->ulp_crc);
  163. pdu_cb->pdulen = ntohs(cpl->len);
  164. if (pdu_cb->flags & PDUCBF_RX_HDR)
  165. pdu_cb->complete = true;
  166. lro_cb->pdu_totallen += pdu_cb->pdulen;
  167. lro_cb->complete = true;
  168. lro_cb->pdu_idx++;
  169. }
  170. static void
  171. cxgbit_copy_frags(struct sk_buff *skb, const struct pkt_gl *gl,
  172. unsigned int offset)
  173. {
  174. u8 skb_frag_idx = skb_shinfo(skb)->nr_frags;
  175. u8 i;
  176. /* usually there's just one frag */
  177. __skb_fill_page_desc(skb, skb_frag_idx, gl->frags[0].page,
  178. gl->frags[0].offset + offset,
  179. gl->frags[0].size - offset);
  180. for (i = 1; i < gl->nfrags; i++)
  181. __skb_fill_page_desc(skb, skb_frag_idx + i,
  182. gl->frags[i].page,
  183. gl->frags[i].offset,
  184. gl->frags[i].size);
  185. skb_shinfo(skb)->nr_frags += gl->nfrags;
  186. /* get a reference to the last page, we don't own it */
  187. get_page(gl->frags[gl->nfrags - 1].page);
  188. }
  189. static void
  190. cxgbit_lro_add_packet_gl(struct sk_buff *skb, u8 op, const struct pkt_gl *gl)
  191. {
  192. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  193. struct cxgbit_lro_pdu_cb *pdu_cb = cxgbit_skb_lro_pdu_cb(skb,
  194. lro_cb->pdu_idx);
  195. u32 len, offset;
  196. if (op == CPL_ISCSI_HDR) {
  197. struct cpl_iscsi_hdr *cpl = (struct cpl_iscsi_hdr *)gl->va;
  198. offset = sizeof(struct cpl_iscsi_hdr);
  199. pdu_cb->flags |= PDUCBF_RX_HDR;
  200. pdu_cb->seq = ntohl(cpl->seq);
  201. len = ntohs(cpl->len);
  202. pdu_cb->hdr = gl->va + offset;
  203. pdu_cb->hlen = len;
  204. pdu_cb->hfrag_idx = skb_shinfo(skb)->nr_frags;
  205. if (unlikely(gl->nfrags > 1))
  206. cxgbit_skcb_flags(skb) = 0;
  207. lro_cb->complete = false;
  208. } else if (op == CPL_ISCSI_DATA) {
  209. struct cpl_iscsi_data *cpl = (struct cpl_iscsi_data *)gl->va;
  210. offset = sizeof(struct cpl_iscsi_data);
  211. pdu_cb->flags |= PDUCBF_RX_DATA;
  212. len = ntohs(cpl->len);
  213. pdu_cb->dlen = len;
  214. pdu_cb->doffset = lro_cb->offset;
  215. pdu_cb->nr_dfrags = gl->nfrags;
  216. pdu_cb->dfrag_idx = skb_shinfo(skb)->nr_frags;
  217. lro_cb->complete = false;
  218. } else {
  219. struct cpl_rx_iscsi_cmp *cpl;
  220. cpl = (struct cpl_rx_iscsi_cmp *)gl->va;
  221. offset = sizeof(struct cpl_rx_iscsi_cmp);
  222. pdu_cb->flags |= (PDUCBF_RX_HDR | PDUCBF_RX_STATUS);
  223. len = be16_to_cpu(cpl->len);
  224. pdu_cb->hdr = gl->va + offset;
  225. pdu_cb->hlen = len;
  226. pdu_cb->hfrag_idx = skb_shinfo(skb)->nr_frags;
  227. pdu_cb->ddigest = be32_to_cpu(cpl->ulp_crc);
  228. pdu_cb->pdulen = ntohs(cpl->len);
  229. if (unlikely(gl->nfrags > 1))
  230. cxgbit_skcb_flags(skb) = 0;
  231. cxgbit_process_ddpvld(lro_cb->csk, pdu_cb,
  232. be32_to_cpu(cpl->ddpvld));
  233. if (pdu_cb->flags & PDUCBF_RX_DATA_DDPD) {
  234. pdu_cb->flags |= PDUCBF_RX_DDP_CMP;
  235. pdu_cb->complete = true;
  236. } else if (pdu_cb->flags & PDUCBF_RX_DATA) {
  237. pdu_cb->complete = true;
  238. }
  239. lro_cb->pdu_totallen += pdu_cb->hlen + pdu_cb->dlen;
  240. lro_cb->complete = true;
  241. lro_cb->pdu_idx++;
  242. }
  243. cxgbit_copy_frags(skb, gl, offset);
  244. pdu_cb->frags += gl->nfrags;
  245. lro_cb->offset += len;
  246. skb->len += len;
  247. skb->data_len += len;
  248. skb->truesize += len;
  249. }
  250. static struct sk_buff *
  251. cxgbit_lro_init_skb(struct cxgbit_sock *csk, u8 op, const struct pkt_gl *gl,
  252. const __be64 *rsp, struct napi_struct *napi)
  253. {
  254. struct sk_buff *skb;
  255. struct cxgbit_lro_cb *lro_cb;
  256. skb = napi_alloc_skb(napi, LRO_SKB_MAX_HEADROOM);
  257. if (unlikely(!skb))
  258. return NULL;
  259. memset(skb->data, 0, LRO_SKB_MAX_HEADROOM);
  260. cxgbit_skcb_flags(skb) |= SKCBF_RX_LRO;
  261. lro_cb = cxgbit_skb_lro_cb(skb);
  262. cxgbit_get_csk(csk);
  263. lro_cb->csk = csk;
  264. return skb;
  265. }
  266. static void cxgbit_queue_lro_skb(struct cxgbit_sock *csk, struct sk_buff *skb)
  267. {
  268. bool wakeup_thread = false;
  269. spin_lock(&csk->rxq.lock);
  270. __skb_queue_tail(&csk->rxq, skb);
  271. if (skb_queue_len(&csk->rxq) == 1)
  272. wakeup_thread = true;
  273. spin_unlock(&csk->rxq.lock);
  274. if (wakeup_thread)
  275. wake_up(&csk->waitq);
  276. }
  277. static void cxgbit_lro_flush(struct t4_lro_mgr *lro_mgr, struct sk_buff *skb)
  278. {
  279. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  280. struct cxgbit_sock *csk = lro_cb->csk;
  281. csk->lro_skb = NULL;
  282. __skb_unlink(skb, &lro_mgr->lroq);
  283. cxgbit_queue_lro_skb(csk, skb);
  284. cxgbit_put_csk(csk);
  285. lro_mgr->lro_pkts++;
  286. lro_mgr->lro_session_cnt--;
  287. }
  288. static void cxgbit_uld_lro_flush(struct t4_lro_mgr *lro_mgr)
  289. {
  290. struct sk_buff *skb;
  291. while ((skb = skb_peek(&lro_mgr->lroq)))
  292. cxgbit_lro_flush(lro_mgr, skb);
  293. }
  294. static int
  295. cxgbit_lro_receive(struct cxgbit_sock *csk, u8 op, const __be64 *rsp,
  296. const struct pkt_gl *gl, struct t4_lro_mgr *lro_mgr,
  297. struct napi_struct *napi)
  298. {
  299. struct sk_buff *skb;
  300. struct cxgbit_lro_cb *lro_cb;
  301. if (!csk) {
  302. pr_err("%s: csk NULL, op 0x%x.\n", __func__, op);
  303. goto out;
  304. }
  305. if (csk->lro_skb)
  306. goto add_packet;
  307. start_lro:
  308. if (lro_mgr->lro_session_cnt >= MAX_LRO_SESSIONS) {
  309. cxgbit_uld_lro_flush(lro_mgr);
  310. goto start_lro;
  311. }
  312. skb = cxgbit_lro_init_skb(csk, op, gl, rsp, napi);
  313. if (unlikely(!skb))
  314. goto out;
  315. csk->lro_skb = skb;
  316. __skb_queue_tail(&lro_mgr->lroq, skb);
  317. lro_mgr->lro_session_cnt++;
  318. add_packet:
  319. skb = csk->lro_skb;
  320. lro_cb = cxgbit_skb_lro_cb(skb);
  321. if ((gl && (((skb_shinfo(skb)->nr_frags + gl->nfrags) >
  322. MAX_SKB_FRAGS) || (lro_cb->pdu_totallen >= LRO_FLUSH_LEN_MAX))) ||
  323. (lro_cb->pdu_idx >= MAX_SKB_FRAGS)) {
  324. cxgbit_lro_flush(lro_mgr, skb);
  325. goto start_lro;
  326. }
  327. if (gl)
  328. cxgbit_lro_add_packet_gl(skb, op, gl);
  329. else
  330. cxgbit_lro_add_packet_rsp(skb, op, rsp);
  331. lro_mgr->lro_merged++;
  332. return 0;
  333. out:
  334. return -1;
  335. }
  336. static int
  337. cxgbit_uld_lro_rx_handler(void *hndl, const __be64 *rsp,
  338. const struct pkt_gl *gl, struct t4_lro_mgr *lro_mgr,
  339. struct napi_struct *napi)
  340. {
  341. struct cxgbit_device *cdev = hndl;
  342. struct cxgb4_lld_info *lldi = &cdev->lldi;
  343. struct cpl_tx_data *rpl = NULL;
  344. struct cxgbit_sock *csk = NULL;
  345. unsigned int tid = 0;
  346. struct sk_buff *skb;
  347. unsigned int op = *(u8 *)rsp;
  348. bool lro_flush = true;
  349. switch (op) {
  350. case CPL_ISCSI_HDR:
  351. case CPL_ISCSI_DATA:
  352. case CPL_RX_ISCSI_CMP:
  353. case CPL_RX_ISCSI_DDP:
  354. case CPL_FW4_ACK:
  355. lro_flush = false;
  356. case CPL_ABORT_RPL_RSS:
  357. case CPL_PASS_ESTABLISH:
  358. case CPL_PEER_CLOSE:
  359. case CPL_CLOSE_CON_RPL:
  360. case CPL_ABORT_REQ_RSS:
  361. case CPL_SET_TCB_RPL:
  362. case CPL_RX_DATA:
  363. rpl = gl ? (struct cpl_tx_data *)gl->va :
  364. (struct cpl_tx_data *)(rsp + 1);
  365. tid = GET_TID(rpl);
  366. csk = lookup_tid(lldi->tids, tid);
  367. break;
  368. default:
  369. break;
  370. }
  371. if (csk && csk->lro_skb && lro_flush)
  372. cxgbit_lro_flush(lro_mgr, csk->lro_skb);
  373. if (!gl) {
  374. unsigned int len;
  375. if (op == CPL_RX_ISCSI_DDP) {
  376. if (!cxgbit_lro_receive(csk, op, rsp, NULL, lro_mgr,
  377. napi))
  378. return 0;
  379. }
  380. len = 64 - sizeof(struct rsp_ctrl) - 8;
  381. skb = napi_alloc_skb(napi, len);
  382. if (!skb)
  383. goto nomem;
  384. __skb_put(skb, len);
  385. skb_copy_to_linear_data(skb, &rsp[1], len);
  386. } else {
  387. if (unlikely(op != *(u8 *)gl->va)) {
  388. pr_info("? FL 0x%p,RSS%#llx,FL %#llx,len %u.\n",
  389. gl->va, be64_to_cpu(*rsp),
  390. get_unaligned_be64(gl->va),
  391. gl->tot_len);
  392. return 0;
  393. }
  394. if ((op == CPL_ISCSI_HDR) || (op == CPL_ISCSI_DATA) ||
  395. (op == CPL_RX_ISCSI_CMP)) {
  396. if (!cxgbit_lro_receive(csk, op, rsp, gl, lro_mgr,
  397. napi))
  398. return 0;
  399. }
  400. #define RX_PULL_LEN 128
  401. skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
  402. if (unlikely(!skb))
  403. goto nomem;
  404. }
  405. rpl = (struct cpl_tx_data *)skb->data;
  406. op = rpl->ot.opcode;
  407. cxgbit_skcb_rx_opcode(skb) = op;
  408. pr_debug("cdev %p, opcode 0x%x(0x%x,0x%x), skb %p.\n",
  409. cdev, op, rpl->ot.opcode_tid,
  410. ntohl(rpl->ot.opcode_tid), skb);
  411. if (op < NUM_CPL_CMDS && cxgbit_cplhandlers[op]) {
  412. cxgbit_cplhandlers[op](cdev, skb);
  413. } else {
  414. pr_err("No handler for opcode 0x%x.\n", op);
  415. __kfree_skb(skb);
  416. }
  417. return 0;
  418. nomem:
  419. pr_err("%s OOM bailing out.\n", __func__);
  420. return 1;
  421. }
  422. #ifdef CONFIG_CHELSIO_T4_DCB
  423. struct cxgbit_dcb_work {
  424. struct dcb_app_type dcb_app;
  425. struct work_struct work;
  426. };
  427. static void
  428. cxgbit_update_dcb_priority(struct cxgbit_device *cdev, u8 port_id,
  429. u8 dcb_priority, u16 port_num)
  430. {
  431. struct cxgbit_sock *csk;
  432. struct sk_buff *skb;
  433. u16 local_port;
  434. bool wakeup_thread = false;
  435. spin_lock_bh(&cdev->cskq.lock);
  436. list_for_each_entry(csk, &cdev->cskq.list, list) {
  437. if (csk->port_id != port_id)
  438. continue;
  439. if (csk->com.local_addr.ss_family == AF_INET6) {
  440. struct sockaddr_in6 *sock_in6;
  441. sock_in6 = (struct sockaddr_in6 *)&csk->com.local_addr;
  442. local_port = ntohs(sock_in6->sin6_port);
  443. } else {
  444. struct sockaddr_in *sock_in;
  445. sock_in = (struct sockaddr_in *)&csk->com.local_addr;
  446. local_port = ntohs(sock_in->sin_port);
  447. }
  448. if (local_port != port_num)
  449. continue;
  450. if (csk->dcb_priority == dcb_priority)
  451. continue;
  452. skb = alloc_skb(0, GFP_ATOMIC);
  453. if (!skb)
  454. continue;
  455. spin_lock(&csk->rxq.lock);
  456. __skb_queue_tail(&csk->rxq, skb);
  457. if (skb_queue_len(&csk->rxq) == 1)
  458. wakeup_thread = true;
  459. spin_unlock(&csk->rxq.lock);
  460. if (wakeup_thread) {
  461. wake_up(&csk->waitq);
  462. wakeup_thread = false;
  463. }
  464. }
  465. spin_unlock_bh(&cdev->cskq.lock);
  466. }
  467. static void cxgbit_dcb_workfn(struct work_struct *work)
  468. {
  469. struct cxgbit_dcb_work *dcb_work;
  470. struct net_device *ndev;
  471. struct cxgbit_device *cdev = NULL;
  472. struct dcb_app_type *iscsi_app;
  473. u8 priority, port_id = 0xff;
  474. dcb_work = container_of(work, struct cxgbit_dcb_work, work);
  475. iscsi_app = &dcb_work->dcb_app;
  476. if (iscsi_app->dcbx & DCB_CAP_DCBX_VER_IEEE) {
  477. if (iscsi_app->app.selector != IEEE_8021QAZ_APP_SEL_ANY)
  478. goto out;
  479. priority = iscsi_app->app.priority;
  480. } else if (iscsi_app->dcbx & DCB_CAP_DCBX_VER_CEE) {
  481. if (iscsi_app->app.selector != DCB_APP_IDTYPE_PORTNUM)
  482. goto out;
  483. if (!iscsi_app->app.priority)
  484. goto out;
  485. priority = ffs(iscsi_app->app.priority) - 1;
  486. } else {
  487. goto out;
  488. }
  489. pr_debug("priority for ifid %d is %u\n",
  490. iscsi_app->ifindex, priority);
  491. ndev = dev_get_by_index(&init_net, iscsi_app->ifindex);
  492. if (!ndev)
  493. goto out;
  494. mutex_lock(&cdev_list_lock);
  495. cdev = cxgbit_find_device(ndev, &port_id);
  496. dev_put(ndev);
  497. if (!cdev) {
  498. mutex_unlock(&cdev_list_lock);
  499. goto out;
  500. }
  501. cxgbit_update_dcb_priority(cdev, port_id, priority,
  502. iscsi_app->app.protocol);
  503. mutex_unlock(&cdev_list_lock);
  504. out:
  505. kfree(dcb_work);
  506. }
  507. static int
  508. cxgbit_dcbevent_notify(struct notifier_block *nb, unsigned long action,
  509. void *data)
  510. {
  511. struct cxgbit_dcb_work *dcb_work;
  512. struct dcb_app_type *dcb_app = data;
  513. dcb_work = kzalloc(sizeof(*dcb_work), GFP_ATOMIC);
  514. if (!dcb_work)
  515. return NOTIFY_DONE;
  516. dcb_work->dcb_app = *dcb_app;
  517. INIT_WORK(&dcb_work->work, cxgbit_dcb_workfn);
  518. schedule_work(&dcb_work->work);
  519. return NOTIFY_OK;
  520. }
  521. #endif
  522. static enum target_prot_op cxgbit_get_sup_prot_ops(struct iscsi_conn *conn)
  523. {
  524. return TARGET_PROT_NORMAL;
  525. }
  526. static struct iscsit_transport cxgbit_transport = {
  527. .name = DRV_NAME,
  528. .transport_type = ISCSI_CXGBIT,
  529. .rdma_shutdown = false,
  530. .priv_size = sizeof(struct cxgbit_cmd),
  531. .owner = THIS_MODULE,
  532. .iscsit_setup_np = cxgbit_setup_np,
  533. .iscsit_accept_np = cxgbit_accept_np,
  534. .iscsit_free_np = cxgbit_free_np,
  535. .iscsit_free_conn = cxgbit_free_conn,
  536. .iscsit_get_login_rx = cxgbit_get_login_rx,
  537. .iscsit_put_login_tx = cxgbit_put_login_tx,
  538. .iscsit_immediate_queue = iscsit_immediate_queue,
  539. .iscsit_response_queue = iscsit_response_queue,
  540. .iscsit_get_dataout = iscsit_build_r2ts_for_cmd,
  541. .iscsit_queue_data_in = iscsit_queue_rsp,
  542. .iscsit_queue_status = iscsit_queue_rsp,
  543. .iscsit_xmit_pdu = cxgbit_xmit_pdu,
  544. .iscsit_get_r2t_ttt = cxgbit_get_r2t_ttt,
  545. .iscsit_get_rx_pdu = cxgbit_get_rx_pdu,
  546. .iscsit_validate_params = cxgbit_validate_params,
  547. .iscsit_release_cmd = cxgbit_release_cmd,
  548. .iscsit_aborted_task = iscsit_aborted_task,
  549. .iscsit_get_sup_prot_ops = cxgbit_get_sup_prot_ops,
  550. };
  551. static struct cxgb4_uld_info cxgbit_uld_info = {
  552. .name = DRV_NAME,
  553. .nrxq = MAX_ULD_QSETS,
  554. .ntxq = MAX_ULD_QSETS,
  555. .rxq_size = 1024,
  556. .lro = true,
  557. .add = cxgbit_uld_add,
  558. .state_change = cxgbit_uld_state_change,
  559. .lro_rx_handler = cxgbit_uld_lro_rx_handler,
  560. .lro_flush = cxgbit_uld_lro_flush,
  561. };
  562. #ifdef CONFIG_CHELSIO_T4_DCB
  563. static struct notifier_block cxgbit_dcbevent_nb = {
  564. .notifier_call = cxgbit_dcbevent_notify,
  565. };
  566. #endif
  567. static int __init cxgbit_init(void)
  568. {
  569. cxgb4_register_uld(CXGB4_ULD_ISCSIT, &cxgbit_uld_info);
  570. iscsit_register_transport(&cxgbit_transport);
  571. #ifdef CONFIG_CHELSIO_T4_DCB
  572. pr_info("%s dcb enabled.\n", DRV_NAME);
  573. register_dcbevent_notifier(&cxgbit_dcbevent_nb);
  574. #endif
  575. BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, cb) <
  576. sizeof(union cxgbit_skb_cb));
  577. return 0;
  578. }
  579. static void __exit cxgbit_exit(void)
  580. {
  581. struct cxgbit_device *cdev, *tmp;
  582. #ifdef CONFIG_CHELSIO_T4_DCB
  583. unregister_dcbevent_notifier(&cxgbit_dcbevent_nb);
  584. #endif
  585. mutex_lock(&cdev_list_lock);
  586. list_for_each_entry_safe(cdev, tmp, &cdev_list_head, list) {
  587. list_del(&cdev->list);
  588. cxgbit_put_cdev(cdev);
  589. }
  590. mutex_unlock(&cdev_list_lock);
  591. iscsit_unregister_transport(&cxgbit_transport);
  592. cxgb4_unregister_uld(CXGB4_ULD_ISCSIT);
  593. }
  594. module_init(cxgbit_init);
  595. module_exit(cxgbit_exit);
  596. MODULE_DESCRIPTION("Chelsio iSCSI target offload driver");
  597. MODULE_AUTHOR("Chelsio Communications");
  598. MODULE_VERSION(DRV_VERSION);
  599. MODULE_LICENSE("GPL");