main.c 9.2 KB

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  1. /*
  2. * Copyright 2014 IBM Corp.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version
  7. * 2 of the License, or (at your option) any later version.
  8. */
  9. #include <linux/spinlock.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/device.h>
  13. #include <linux/mutex.h>
  14. #include <linux/init.h>
  15. #include <linux/list.h>
  16. #include <linux/mm.h>
  17. #include <linux/of.h>
  18. #include <linux/slab.h>
  19. #include <linux/idr.h>
  20. #include <linux/pci.h>
  21. #include <linux/sched/task.h>
  22. #include <asm/cputable.h>
  23. #include <misc/cxl-base.h>
  24. #include "cxl.h"
  25. #include "trace.h"
  26. static DEFINE_SPINLOCK(adapter_idr_lock);
  27. static DEFINE_IDR(cxl_adapter_idr);
  28. uint cxl_verbose;
  29. module_param_named(verbose, cxl_verbose, uint, 0600);
  30. MODULE_PARM_DESC(verbose, "Enable verbose dmesg output");
  31. const struct cxl_backend_ops *cxl_ops;
  32. int cxl_afu_slbia(struct cxl_afu *afu)
  33. {
  34. unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
  35. pr_devel("cxl_afu_slbia issuing SLBIA command\n");
  36. cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
  37. while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
  38. if (time_after_eq(jiffies, timeout)) {
  39. dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
  40. return -EBUSY;
  41. }
  42. /* If the adapter has gone down, we can assume that we
  43. * will PERST it and that will invalidate everything.
  44. */
  45. if (!cxl_ops->link_ok(afu->adapter, afu))
  46. return -EIO;
  47. cpu_relax();
  48. }
  49. return 0;
  50. }
  51. static inline void _cxl_slbia(struct cxl_context *ctx, struct mm_struct *mm)
  52. {
  53. unsigned long flags;
  54. if (ctx->mm != mm)
  55. return;
  56. pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__,
  57. ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe);
  58. spin_lock_irqsave(&ctx->sste_lock, flags);
  59. trace_cxl_slbia(ctx);
  60. memset(ctx->sstp, 0, ctx->sst_size);
  61. spin_unlock_irqrestore(&ctx->sste_lock, flags);
  62. mb();
  63. cxl_afu_slbia(ctx->afu);
  64. }
  65. static inline void cxl_slbia_core(struct mm_struct *mm)
  66. {
  67. struct cxl *adapter;
  68. struct cxl_afu *afu;
  69. struct cxl_context *ctx;
  70. int card, slice, id;
  71. pr_devel("%s called\n", __func__);
  72. spin_lock(&adapter_idr_lock);
  73. idr_for_each_entry(&cxl_adapter_idr, adapter, card) {
  74. /* XXX: Make this lookup faster with link from mm to ctx */
  75. spin_lock(&adapter->afu_list_lock);
  76. for (slice = 0; slice < adapter->slices; slice++) {
  77. afu = adapter->afu[slice];
  78. if (!afu || !afu->enabled)
  79. continue;
  80. rcu_read_lock();
  81. idr_for_each_entry(&afu->contexts_idr, ctx, id)
  82. _cxl_slbia(ctx, mm);
  83. rcu_read_unlock();
  84. }
  85. spin_unlock(&adapter->afu_list_lock);
  86. }
  87. spin_unlock(&adapter_idr_lock);
  88. }
  89. static struct cxl_calls cxl_calls = {
  90. .cxl_slbia = cxl_slbia_core,
  91. .cxl_pci_associate_default_context = _cxl_pci_associate_default_context,
  92. .cxl_pci_disable_device = _cxl_pci_disable_device,
  93. .cxl_next_msi_hwirq = _cxl_next_msi_hwirq,
  94. .cxl_cx4_setup_msi_irqs = _cxl_cx4_setup_msi_irqs,
  95. .cxl_cx4_teardown_msi_irqs = _cxl_cx4_teardown_msi_irqs,
  96. .owner = THIS_MODULE,
  97. };
  98. int cxl_alloc_sst(struct cxl_context *ctx)
  99. {
  100. unsigned long vsid;
  101. u64 ea_mask, size, sstp0, sstp1;
  102. sstp0 = 0;
  103. sstp1 = 0;
  104. ctx->sst_size = PAGE_SIZE;
  105. ctx->sst_lru = 0;
  106. ctx->sstp = (struct cxl_sste *)get_zeroed_page(GFP_KERNEL);
  107. if (!ctx->sstp) {
  108. pr_err("cxl_alloc_sst: Unable to allocate segment table\n");
  109. return -ENOMEM;
  110. }
  111. pr_devel("SSTP allocated at 0x%p\n", ctx->sstp);
  112. vsid = get_kernel_vsid((u64)ctx->sstp, mmu_kernel_ssize) << 12;
  113. sstp0 |= (u64)mmu_kernel_ssize << CXL_SSTP0_An_B_SHIFT;
  114. sstp0 |= (SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp) << 50;
  115. size = (((u64)ctx->sst_size >> 8) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT;
  116. if (unlikely(size & ~CXL_SSTP0_An_SegTableSize_MASK)) {
  117. WARN(1, "Impossible segment table size\n");
  118. return -EINVAL;
  119. }
  120. sstp0 |= size;
  121. if (mmu_kernel_ssize == MMU_SEGSIZE_256M)
  122. ea_mask = 0xfffff00ULL;
  123. else
  124. ea_mask = 0xffffffff00ULL;
  125. sstp0 |= vsid >> (50-14); /* Top 14 bits of VSID */
  126. sstp1 |= (vsid << (64-(50-14))) & ~ea_mask;
  127. sstp1 |= (u64)ctx->sstp & ea_mask;
  128. sstp1 |= CXL_SSTP1_An_V;
  129. pr_devel("Looked up %#llx: slbfee. %#llx (ssize: %x, vsid: %#lx), copied to SSTP0: %#llx, SSTP1: %#llx\n",
  130. (u64)ctx->sstp, (u64)ctx->sstp & ESID_MASK, mmu_kernel_ssize, vsid, sstp0, sstp1);
  131. /* Store calculated sstp hardware points for use later */
  132. ctx->sstp0 = sstp0;
  133. ctx->sstp1 = sstp1;
  134. return 0;
  135. }
  136. /* print buffer content as integers when debugging */
  137. void cxl_dump_debug_buffer(void *buf, size_t buf_len)
  138. {
  139. #ifdef DEBUG
  140. int i, *ptr;
  141. /*
  142. * We want to regroup up to 4 integers per line, which means they
  143. * need to be in the same pr_devel() statement
  144. */
  145. ptr = (int *) buf;
  146. for (i = 0; i * 4 < buf_len; i += 4) {
  147. if ((i + 3) * 4 < buf_len)
  148. pr_devel("%.8x %.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
  149. ptr[i + 2], ptr[i + 3]);
  150. else if ((i + 2) * 4 < buf_len)
  151. pr_devel("%.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
  152. ptr[i + 2]);
  153. else if ((i + 1) * 4 < buf_len)
  154. pr_devel("%.8x %.8x\n", ptr[i], ptr[i + 1]);
  155. else
  156. pr_devel("%.8x\n", ptr[i]);
  157. }
  158. #endif /* DEBUG */
  159. }
  160. /* Find a CXL adapter by it's number and increase it's refcount */
  161. struct cxl *get_cxl_adapter(int num)
  162. {
  163. struct cxl *adapter;
  164. spin_lock(&adapter_idr_lock);
  165. if ((adapter = idr_find(&cxl_adapter_idr, num)))
  166. get_device(&adapter->dev);
  167. spin_unlock(&adapter_idr_lock);
  168. return adapter;
  169. }
  170. static int cxl_alloc_adapter_nr(struct cxl *adapter)
  171. {
  172. int i;
  173. idr_preload(GFP_KERNEL);
  174. spin_lock(&adapter_idr_lock);
  175. i = idr_alloc(&cxl_adapter_idr, adapter, 0, 0, GFP_NOWAIT);
  176. spin_unlock(&adapter_idr_lock);
  177. idr_preload_end();
  178. if (i < 0)
  179. return i;
  180. adapter->adapter_num = i;
  181. return 0;
  182. }
  183. void cxl_remove_adapter_nr(struct cxl *adapter)
  184. {
  185. idr_remove(&cxl_adapter_idr, adapter->adapter_num);
  186. }
  187. struct cxl *cxl_alloc_adapter(void)
  188. {
  189. struct cxl *adapter;
  190. if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
  191. return NULL;
  192. spin_lock_init(&adapter->afu_list_lock);
  193. if (cxl_alloc_adapter_nr(adapter))
  194. goto err1;
  195. if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
  196. goto err2;
  197. /* start with context lock taken */
  198. atomic_set(&adapter->contexts_num, -1);
  199. return adapter;
  200. err2:
  201. cxl_remove_adapter_nr(adapter);
  202. err1:
  203. kfree(adapter);
  204. return NULL;
  205. }
  206. struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
  207. {
  208. struct cxl_afu *afu;
  209. if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
  210. return NULL;
  211. afu->adapter = adapter;
  212. afu->dev.parent = &adapter->dev;
  213. afu->dev.release = cxl_ops->release_afu;
  214. afu->slice = slice;
  215. idr_init(&afu->contexts_idr);
  216. mutex_init(&afu->contexts_lock);
  217. spin_lock_init(&afu->afu_cntl_lock);
  218. atomic_set(&afu->configured_state, -1);
  219. afu->prefault_mode = CXL_PREFAULT_NONE;
  220. afu->irqs_max = afu->adapter->user_irqs;
  221. return afu;
  222. }
  223. int cxl_afu_select_best_mode(struct cxl_afu *afu)
  224. {
  225. if (afu->modes_supported & CXL_MODE_DIRECTED)
  226. return cxl_ops->afu_activate_mode(afu, CXL_MODE_DIRECTED);
  227. if (afu->modes_supported & CXL_MODE_DEDICATED)
  228. return cxl_ops->afu_activate_mode(afu, CXL_MODE_DEDICATED);
  229. dev_warn(&afu->dev, "No supported programming modes available\n");
  230. /* We don't fail this so the user can inspect sysfs */
  231. return 0;
  232. }
  233. int cxl_adapter_context_get(struct cxl *adapter)
  234. {
  235. int rc;
  236. rc = atomic_inc_unless_negative(&adapter->contexts_num);
  237. return rc ? 0 : -EBUSY;
  238. }
  239. void cxl_adapter_context_put(struct cxl *adapter)
  240. {
  241. atomic_dec_if_positive(&adapter->contexts_num);
  242. }
  243. int cxl_adapter_context_lock(struct cxl *adapter)
  244. {
  245. int rc;
  246. /* no active contexts -> contexts_num == 0 */
  247. rc = atomic_cmpxchg(&adapter->contexts_num, 0, -1);
  248. return rc ? -EBUSY : 0;
  249. }
  250. void cxl_adapter_context_unlock(struct cxl *adapter)
  251. {
  252. int val = atomic_cmpxchg(&adapter->contexts_num, -1, 0);
  253. /*
  254. * contexts lock taken -> contexts_num == -1
  255. * If not true then show a warning and force reset the lock.
  256. * This will happen when context_unlock was requested without
  257. * doing a context_lock.
  258. */
  259. if (val != -1) {
  260. atomic_set(&adapter->contexts_num, 0);
  261. WARN(1, "Adapter context unlocked with %d active contexts",
  262. val);
  263. }
  264. }
  265. static int __init init_cxl(void)
  266. {
  267. int rc = 0;
  268. if ((rc = cxl_file_init()))
  269. return rc;
  270. cxl_debugfs_init();
  271. /*
  272. * we don't register the callback on P9. slb callack is only
  273. * used for the PSL8 MMU and CX4.
  274. */
  275. if (cxl_is_power8()) {
  276. rc = register_cxl_calls(&cxl_calls);
  277. if (rc)
  278. goto err;
  279. }
  280. if (cpu_has_feature(CPU_FTR_HVMODE)) {
  281. cxl_ops = &cxl_native_ops;
  282. rc = pci_register_driver(&cxl_pci_driver);
  283. }
  284. #ifdef CONFIG_PPC_PSERIES
  285. else {
  286. cxl_ops = &cxl_guest_ops;
  287. rc = platform_driver_register(&cxl_of_driver);
  288. }
  289. #endif
  290. if (rc)
  291. goto err1;
  292. return 0;
  293. err1:
  294. if (cxl_is_power8())
  295. unregister_cxl_calls(&cxl_calls);
  296. err:
  297. cxl_debugfs_exit();
  298. cxl_file_exit();
  299. return rc;
  300. }
  301. static void exit_cxl(void)
  302. {
  303. if (cpu_has_feature(CPU_FTR_HVMODE))
  304. pci_unregister_driver(&cxl_pci_driver);
  305. #ifdef CONFIG_PPC_PSERIES
  306. else
  307. platform_driver_unregister(&cxl_of_driver);
  308. #endif
  309. cxl_debugfs_exit();
  310. cxl_file_exit();
  311. if (cxl_is_power8())
  312. unregister_cxl_calls(&cxl_calls);
  313. idr_destroy(&cxl_adapter_idr);
  314. }
  315. module_init(init_cxl);
  316. module_exit(exit_cxl);
  317. MODULE_DESCRIPTION("IBM Coherent Accelerator");
  318. MODULE_AUTHOR("Ian Munsie <imunsie@au1.ibm.com>");
  319. MODULE_LICENSE("GPL");