mxl5007t.c 21 KB

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  1. /*
  2. * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
  3. *
  4. * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/i2c.h>
  17. #include <linux/types.h>
  18. #include <linux/videodev2.h>
  19. #include "tuner-i2c.h"
  20. #include "mxl5007t.h"
  21. static DEFINE_MUTEX(mxl5007t_list_mutex);
  22. static LIST_HEAD(hybrid_tuner_instance_list);
  23. static int mxl5007t_debug;
  24. module_param_named(debug, mxl5007t_debug, int, 0644);
  25. MODULE_PARM_DESC(debug, "set debug level");
  26. /* ------------------------------------------------------------------------- */
  27. #define mxl_printk(kern, fmt, arg...) \
  28. printk(kern "%s: " fmt "\n", __func__, ##arg)
  29. #define mxl_err(fmt, arg...) \
  30. mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
  31. #define mxl_warn(fmt, arg...) \
  32. mxl_printk(KERN_WARNING, fmt, ##arg)
  33. #define mxl_info(fmt, arg...) \
  34. mxl_printk(KERN_INFO, fmt, ##arg)
  35. #define mxl_debug(fmt, arg...) \
  36. ({ \
  37. if (mxl5007t_debug) \
  38. mxl_printk(KERN_DEBUG, fmt, ##arg); \
  39. })
  40. #define mxl_fail(ret) \
  41. ({ \
  42. int __ret; \
  43. __ret = (ret < 0); \
  44. if (__ret) \
  45. mxl_printk(KERN_ERR, "error %d on line %d", \
  46. ret, __LINE__); \
  47. __ret; \
  48. })
  49. /* ------------------------------------------------------------------------- */
  50. #define MHz 1000000
  51. enum mxl5007t_mode {
  52. MxL_MODE_ISDBT = 0,
  53. MxL_MODE_DVBT = 1,
  54. MxL_MODE_ATSC = 2,
  55. MxL_MODE_CABLE = 0x10,
  56. };
  57. enum mxl5007t_chip_version {
  58. MxL_UNKNOWN_ID = 0x00,
  59. MxL_5007_V1_F1 = 0x11,
  60. MxL_5007_V1_F2 = 0x12,
  61. MxL_5007_V4 = 0x14,
  62. MxL_5007_V2_100_F1 = 0x21,
  63. MxL_5007_V2_100_F2 = 0x22,
  64. MxL_5007_V2_200_F1 = 0x23,
  65. MxL_5007_V2_200_F2 = 0x24,
  66. };
  67. struct reg_pair_t {
  68. u8 reg;
  69. u8 val;
  70. };
  71. /* ------------------------------------------------------------------------- */
  72. static struct reg_pair_t init_tab[] = {
  73. { 0x02, 0x06 },
  74. { 0x03, 0x48 },
  75. { 0x05, 0x04 },
  76. { 0x06, 0x10 },
  77. { 0x2e, 0x15 }, /* OVERRIDE */
  78. { 0x30, 0x10 }, /* OVERRIDE */
  79. { 0x45, 0x58 }, /* OVERRIDE */
  80. { 0x48, 0x19 }, /* OVERRIDE */
  81. { 0x52, 0x03 }, /* OVERRIDE */
  82. { 0x53, 0x44 }, /* OVERRIDE */
  83. { 0x6a, 0x4b }, /* OVERRIDE */
  84. { 0x76, 0x00 }, /* OVERRIDE */
  85. { 0x78, 0x18 }, /* OVERRIDE */
  86. { 0x7a, 0x17 }, /* OVERRIDE */
  87. { 0x85, 0x06 }, /* OVERRIDE */
  88. { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
  89. { 0, 0 }
  90. };
  91. static struct reg_pair_t init_tab_cable[] = {
  92. { 0x02, 0x06 },
  93. { 0x03, 0x48 },
  94. { 0x05, 0x04 },
  95. { 0x06, 0x10 },
  96. { 0x09, 0x3f },
  97. { 0x0a, 0x3f },
  98. { 0x0b, 0x3f },
  99. { 0x2e, 0x15 }, /* OVERRIDE */
  100. { 0x30, 0x10 }, /* OVERRIDE */
  101. { 0x45, 0x58 }, /* OVERRIDE */
  102. { 0x48, 0x19 }, /* OVERRIDE */
  103. { 0x52, 0x03 }, /* OVERRIDE */
  104. { 0x53, 0x44 }, /* OVERRIDE */
  105. { 0x6a, 0x4b }, /* OVERRIDE */
  106. { 0x76, 0x00 }, /* OVERRIDE */
  107. { 0x78, 0x18 }, /* OVERRIDE */
  108. { 0x7a, 0x17 }, /* OVERRIDE */
  109. { 0x85, 0x06 }, /* OVERRIDE */
  110. { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
  111. { 0, 0 }
  112. };
  113. /* ------------------------------------------------------------------------- */
  114. static struct reg_pair_t reg_pair_rftune[] = {
  115. { 0x0f, 0x00 }, /* abort tune */
  116. { 0x0c, 0x15 },
  117. { 0x0d, 0x40 },
  118. { 0x0e, 0x0e },
  119. { 0x1f, 0x87 }, /* OVERRIDE */
  120. { 0x20, 0x1f }, /* OVERRIDE */
  121. { 0x21, 0x87 }, /* OVERRIDE */
  122. { 0x22, 0x1f }, /* OVERRIDE */
  123. { 0x80, 0x01 }, /* freq dependent */
  124. { 0x0f, 0x01 }, /* start tune */
  125. { 0, 0 }
  126. };
  127. /* ------------------------------------------------------------------------- */
  128. struct mxl5007t_state {
  129. struct list_head hybrid_tuner_instance_list;
  130. struct tuner_i2c_props i2c_props;
  131. struct mutex lock;
  132. struct mxl5007t_config *config;
  133. enum mxl5007t_chip_version chip_id;
  134. struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
  135. struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
  136. struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
  137. enum mxl5007t_if_freq if_freq;
  138. u32 frequency;
  139. u32 bandwidth;
  140. };
  141. /* ------------------------------------------------------------------------- */
  142. /* called by _init and _rftun to manipulate the register arrays */
  143. static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
  144. {
  145. unsigned int i = 0;
  146. while (reg_pair[i].reg || reg_pair[i].val) {
  147. if (reg_pair[i].reg == reg) {
  148. reg_pair[i].val &= ~mask;
  149. reg_pair[i].val |= val;
  150. }
  151. i++;
  152. }
  153. return;
  154. }
  155. static void copy_reg_bits(struct reg_pair_t *reg_pair1,
  156. struct reg_pair_t *reg_pair2)
  157. {
  158. unsigned int i, j;
  159. i = j = 0;
  160. while (reg_pair1[i].reg || reg_pair1[i].val) {
  161. while (reg_pair2[j].reg || reg_pair2[j].val) {
  162. if (reg_pair1[i].reg != reg_pair2[j].reg) {
  163. j++;
  164. continue;
  165. }
  166. reg_pair2[j].val = reg_pair1[i].val;
  167. break;
  168. }
  169. i++;
  170. }
  171. return;
  172. }
  173. /* ------------------------------------------------------------------------- */
  174. static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
  175. enum mxl5007t_mode mode,
  176. s32 if_diff_out_level)
  177. {
  178. switch (mode) {
  179. case MxL_MODE_ATSC:
  180. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
  181. break;
  182. case MxL_MODE_DVBT:
  183. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
  184. break;
  185. case MxL_MODE_ISDBT:
  186. set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
  187. break;
  188. case MxL_MODE_CABLE:
  189. set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
  190. set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
  191. 8 - if_diff_out_level);
  192. set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
  193. break;
  194. default:
  195. mxl_fail(-EINVAL);
  196. }
  197. return;
  198. }
  199. static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
  200. enum mxl5007t_if_freq if_freq,
  201. int invert_if)
  202. {
  203. u8 val;
  204. switch (if_freq) {
  205. case MxL_IF_4_MHZ:
  206. val = 0x00;
  207. break;
  208. case MxL_IF_4_5_MHZ:
  209. val = 0x02;
  210. break;
  211. case MxL_IF_4_57_MHZ:
  212. val = 0x03;
  213. break;
  214. case MxL_IF_5_MHZ:
  215. val = 0x04;
  216. break;
  217. case MxL_IF_5_38_MHZ:
  218. val = 0x05;
  219. break;
  220. case MxL_IF_6_MHZ:
  221. val = 0x06;
  222. break;
  223. case MxL_IF_6_28_MHZ:
  224. val = 0x07;
  225. break;
  226. case MxL_IF_9_1915_MHZ:
  227. val = 0x08;
  228. break;
  229. case MxL_IF_35_25_MHZ:
  230. val = 0x09;
  231. break;
  232. case MxL_IF_36_15_MHZ:
  233. val = 0x0a;
  234. break;
  235. case MxL_IF_44_MHZ:
  236. val = 0x0b;
  237. break;
  238. default:
  239. mxl_fail(-EINVAL);
  240. return;
  241. }
  242. set_reg_bits(state->tab_init, 0x02, 0x0f, val);
  243. /* set inverted IF or normal IF */
  244. set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
  245. state->if_freq = if_freq;
  246. return;
  247. }
  248. static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
  249. enum mxl5007t_xtal_freq xtal_freq)
  250. {
  251. switch (xtal_freq) {
  252. case MxL_XTAL_16_MHZ:
  253. /* select xtal freq & ref freq */
  254. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
  255. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
  256. break;
  257. case MxL_XTAL_20_MHZ:
  258. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
  259. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
  260. break;
  261. case MxL_XTAL_20_25_MHZ:
  262. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
  263. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
  264. break;
  265. case MxL_XTAL_20_48_MHZ:
  266. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
  267. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
  268. break;
  269. case MxL_XTAL_24_MHZ:
  270. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
  271. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
  272. break;
  273. case MxL_XTAL_25_MHZ:
  274. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
  275. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
  276. break;
  277. case MxL_XTAL_25_14_MHZ:
  278. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
  279. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
  280. break;
  281. case MxL_XTAL_27_MHZ:
  282. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
  283. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
  284. break;
  285. case MxL_XTAL_28_8_MHZ:
  286. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
  287. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
  288. break;
  289. case MxL_XTAL_32_MHZ:
  290. set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
  291. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
  292. break;
  293. case MxL_XTAL_40_MHZ:
  294. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
  295. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
  296. break;
  297. case MxL_XTAL_44_MHZ:
  298. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
  299. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
  300. break;
  301. case MxL_XTAL_48_MHZ:
  302. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
  303. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
  304. break;
  305. case MxL_XTAL_49_3811_MHZ:
  306. set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
  307. set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
  308. break;
  309. default:
  310. mxl_fail(-EINVAL);
  311. return;
  312. }
  313. return;
  314. }
  315. static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
  316. enum mxl5007t_mode mode)
  317. {
  318. struct mxl5007t_config *cfg = state->config;
  319. memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
  320. memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
  321. mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
  322. mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
  323. mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
  324. set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
  325. set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
  326. if (mode >= MxL_MODE_CABLE) {
  327. copy_reg_bits(state->tab_init, state->tab_init_cable);
  328. return state->tab_init_cable;
  329. } else
  330. return state->tab_init;
  331. }
  332. /* ------------------------------------------------------------------------- */
  333. enum mxl5007t_bw_mhz {
  334. MxL_BW_6MHz = 6,
  335. MxL_BW_7MHz = 7,
  336. MxL_BW_8MHz = 8,
  337. };
  338. static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
  339. enum mxl5007t_bw_mhz bw)
  340. {
  341. u8 val;
  342. switch (bw) {
  343. case MxL_BW_6MHz:
  344. val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
  345. * and DIG_MODEINDEX_CSF */
  346. break;
  347. case MxL_BW_7MHz:
  348. val = 0x2a;
  349. break;
  350. case MxL_BW_8MHz:
  351. val = 0x3f;
  352. break;
  353. default:
  354. mxl_fail(-EINVAL);
  355. return;
  356. }
  357. set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
  358. return;
  359. }
  360. static struct
  361. reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
  362. u32 rf_freq, enum mxl5007t_bw_mhz bw)
  363. {
  364. u32 dig_rf_freq = 0;
  365. u32 temp;
  366. u32 frac_divider = 1000000;
  367. unsigned int i;
  368. memcpy(&state->tab_rftune, &reg_pair_rftune, sizeof(reg_pair_rftune));
  369. mxl5007t_set_bw_bits(state, bw);
  370. /* Convert RF frequency into 16 bits =>
  371. * 10 bit integer (MHz) + 6 bit fraction */
  372. dig_rf_freq = rf_freq / MHz;
  373. temp = rf_freq % MHz;
  374. for (i = 0; i < 6; i++) {
  375. dig_rf_freq <<= 1;
  376. frac_divider /= 2;
  377. if (temp > frac_divider) {
  378. temp -= frac_divider;
  379. dig_rf_freq++;
  380. }
  381. }
  382. /* add to have shift center point by 7.8124 kHz */
  383. if (temp > 7812)
  384. dig_rf_freq++;
  385. set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
  386. set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
  387. if (rf_freq >= 333000000)
  388. set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
  389. return state->tab_rftune;
  390. }
  391. /* ------------------------------------------------------------------------- */
  392. static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
  393. {
  394. u8 buf[] = { reg, val };
  395. struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
  396. .buf = buf, .len = 2 };
  397. int ret;
  398. ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
  399. if (ret != 1) {
  400. mxl_err("failed!");
  401. return -EREMOTEIO;
  402. }
  403. return 0;
  404. }
  405. static int mxl5007t_write_regs(struct mxl5007t_state *state,
  406. struct reg_pair_t *reg_pair)
  407. {
  408. unsigned int i = 0;
  409. int ret = 0;
  410. while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
  411. ret = mxl5007t_write_reg(state,
  412. reg_pair[i].reg, reg_pair[i].val);
  413. i++;
  414. }
  415. return ret;
  416. }
  417. static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
  418. {
  419. u8 buf[2] = { 0xfb, reg };
  420. struct i2c_msg msg[] = {
  421. { .addr = state->i2c_props.addr, .flags = 0,
  422. .buf = buf, .len = 2 },
  423. { .addr = state->i2c_props.addr, .flags = I2C_M_RD,
  424. .buf = val, .len = 1 },
  425. };
  426. int ret;
  427. ret = i2c_transfer(state->i2c_props.adap, msg, 2);
  428. if (ret != 2) {
  429. mxl_err("failed!");
  430. return -EREMOTEIO;
  431. }
  432. return 0;
  433. }
  434. static int mxl5007t_soft_reset(struct mxl5007t_state *state)
  435. {
  436. u8 d = 0xff;
  437. struct i2c_msg msg = {
  438. .addr = state->i2c_props.addr, .flags = 0,
  439. .buf = &d, .len = 1
  440. };
  441. int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
  442. if (ret != 1) {
  443. mxl_err("failed!");
  444. return -EREMOTEIO;
  445. }
  446. return 0;
  447. }
  448. static int mxl5007t_tuner_init(struct mxl5007t_state *state,
  449. enum mxl5007t_mode mode)
  450. {
  451. struct reg_pair_t *init_regs;
  452. int ret;
  453. /* calculate initialization reg array */
  454. init_regs = mxl5007t_calc_init_regs(state, mode);
  455. ret = mxl5007t_write_regs(state, init_regs);
  456. if (mxl_fail(ret))
  457. goto fail;
  458. mdelay(1);
  459. fail:
  460. return ret;
  461. }
  462. static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
  463. enum mxl5007t_bw_mhz bw)
  464. {
  465. struct reg_pair_t *rf_tune_regs;
  466. int ret;
  467. /* calculate channel change reg array */
  468. rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
  469. ret = mxl5007t_write_regs(state, rf_tune_regs);
  470. if (mxl_fail(ret))
  471. goto fail;
  472. msleep(3);
  473. fail:
  474. return ret;
  475. }
  476. /* ------------------------------------------------------------------------- */
  477. static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
  478. int *rf_locked, int *ref_locked)
  479. {
  480. u8 d;
  481. int ret;
  482. *rf_locked = 0;
  483. *ref_locked = 0;
  484. ret = mxl5007t_read_reg(state, 0xd8, &d);
  485. if (mxl_fail(ret))
  486. goto fail;
  487. if ((d & 0x0c) == 0x0c)
  488. *rf_locked = 1;
  489. if ((d & 0x03) == 0x03)
  490. *ref_locked = 1;
  491. fail:
  492. return ret;
  493. }
  494. /* ------------------------------------------------------------------------- */
  495. static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
  496. {
  497. struct mxl5007t_state *state = fe->tuner_priv;
  498. int rf_locked, ref_locked, ret;
  499. *status = 0;
  500. if (fe->ops.i2c_gate_ctrl)
  501. fe->ops.i2c_gate_ctrl(fe, 1);
  502. ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
  503. if (mxl_fail(ret))
  504. goto fail;
  505. mxl_debug("%s%s", rf_locked ? "rf locked " : "",
  506. ref_locked ? "ref locked" : "");
  507. if ((rf_locked) || (ref_locked))
  508. *status |= TUNER_STATUS_LOCKED;
  509. fail:
  510. if (fe->ops.i2c_gate_ctrl)
  511. fe->ops.i2c_gate_ctrl(fe, 0);
  512. return ret;
  513. }
  514. /* ------------------------------------------------------------------------- */
  515. static int mxl5007t_set_params(struct dvb_frontend *fe)
  516. {
  517. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  518. u32 delsys = c->delivery_system;
  519. struct mxl5007t_state *state = fe->tuner_priv;
  520. enum mxl5007t_bw_mhz bw;
  521. enum mxl5007t_mode mode;
  522. int ret;
  523. u32 freq = c->frequency;
  524. switch (delsys) {
  525. case SYS_ATSC:
  526. mode = MxL_MODE_ATSC;
  527. bw = MxL_BW_6MHz;
  528. break;
  529. case SYS_DVBC_ANNEX_B:
  530. mode = MxL_MODE_CABLE;
  531. bw = MxL_BW_6MHz;
  532. break;
  533. case SYS_DVBT:
  534. case SYS_DVBT2:
  535. mode = MxL_MODE_DVBT;
  536. switch (c->bandwidth_hz) {
  537. case 6000000:
  538. bw = MxL_BW_6MHz;
  539. break;
  540. case 7000000:
  541. bw = MxL_BW_7MHz;
  542. break;
  543. case 8000000:
  544. bw = MxL_BW_8MHz;
  545. break;
  546. default:
  547. return -EINVAL;
  548. }
  549. break;
  550. default:
  551. mxl_err("modulation type not supported!");
  552. return -EINVAL;
  553. }
  554. if (fe->ops.i2c_gate_ctrl)
  555. fe->ops.i2c_gate_ctrl(fe, 1);
  556. mutex_lock(&state->lock);
  557. ret = mxl5007t_tuner_init(state, mode);
  558. if (mxl_fail(ret))
  559. goto fail;
  560. ret = mxl5007t_tuner_rf_tune(state, freq, bw);
  561. if (mxl_fail(ret))
  562. goto fail;
  563. state->frequency = freq;
  564. state->bandwidth = c->bandwidth_hz;
  565. fail:
  566. mutex_unlock(&state->lock);
  567. if (fe->ops.i2c_gate_ctrl)
  568. fe->ops.i2c_gate_ctrl(fe, 0);
  569. return ret;
  570. }
  571. /* ------------------------------------------------------------------------- */
  572. static int mxl5007t_init(struct dvb_frontend *fe)
  573. {
  574. struct mxl5007t_state *state = fe->tuner_priv;
  575. int ret;
  576. if (fe->ops.i2c_gate_ctrl)
  577. fe->ops.i2c_gate_ctrl(fe, 1);
  578. /* wake from standby */
  579. ret = mxl5007t_write_reg(state, 0x01, 0x01);
  580. mxl_fail(ret);
  581. if (fe->ops.i2c_gate_ctrl)
  582. fe->ops.i2c_gate_ctrl(fe, 0);
  583. return ret;
  584. }
  585. static int mxl5007t_sleep(struct dvb_frontend *fe)
  586. {
  587. struct mxl5007t_state *state = fe->tuner_priv;
  588. int ret;
  589. if (fe->ops.i2c_gate_ctrl)
  590. fe->ops.i2c_gate_ctrl(fe, 1);
  591. /* enter standby mode */
  592. ret = mxl5007t_write_reg(state, 0x01, 0x00);
  593. mxl_fail(ret);
  594. ret = mxl5007t_write_reg(state, 0x0f, 0x00);
  595. mxl_fail(ret);
  596. if (fe->ops.i2c_gate_ctrl)
  597. fe->ops.i2c_gate_ctrl(fe, 0);
  598. return ret;
  599. }
  600. /* ------------------------------------------------------------------------- */
  601. static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
  602. {
  603. struct mxl5007t_state *state = fe->tuner_priv;
  604. *frequency = state->frequency;
  605. return 0;
  606. }
  607. static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  608. {
  609. struct mxl5007t_state *state = fe->tuner_priv;
  610. *bandwidth = state->bandwidth;
  611. return 0;
  612. }
  613. static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  614. {
  615. struct mxl5007t_state *state = fe->tuner_priv;
  616. *frequency = 0;
  617. switch (state->if_freq) {
  618. case MxL_IF_4_MHZ:
  619. *frequency = 4000000;
  620. break;
  621. case MxL_IF_4_5_MHZ:
  622. *frequency = 4500000;
  623. break;
  624. case MxL_IF_4_57_MHZ:
  625. *frequency = 4570000;
  626. break;
  627. case MxL_IF_5_MHZ:
  628. *frequency = 5000000;
  629. break;
  630. case MxL_IF_5_38_MHZ:
  631. *frequency = 5380000;
  632. break;
  633. case MxL_IF_6_MHZ:
  634. *frequency = 6000000;
  635. break;
  636. case MxL_IF_6_28_MHZ:
  637. *frequency = 6280000;
  638. break;
  639. case MxL_IF_9_1915_MHZ:
  640. *frequency = 9191500;
  641. break;
  642. case MxL_IF_35_25_MHZ:
  643. *frequency = 35250000;
  644. break;
  645. case MxL_IF_36_15_MHZ:
  646. *frequency = 36150000;
  647. break;
  648. case MxL_IF_44_MHZ:
  649. *frequency = 44000000;
  650. break;
  651. }
  652. return 0;
  653. }
  654. static void mxl5007t_release(struct dvb_frontend *fe)
  655. {
  656. struct mxl5007t_state *state = fe->tuner_priv;
  657. mutex_lock(&mxl5007t_list_mutex);
  658. if (state)
  659. hybrid_tuner_release_state(state);
  660. mutex_unlock(&mxl5007t_list_mutex);
  661. fe->tuner_priv = NULL;
  662. }
  663. /* ------------------------------------------------------------------------- */
  664. static const struct dvb_tuner_ops mxl5007t_tuner_ops = {
  665. .info = {
  666. .name = "MaxLinear MxL5007T",
  667. },
  668. .init = mxl5007t_init,
  669. .sleep = mxl5007t_sleep,
  670. .set_params = mxl5007t_set_params,
  671. .get_status = mxl5007t_get_status,
  672. .get_frequency = mxl5007t_get_frequency,
  673. .get_bandwidth = mxl5007t_get_bandwidth,
  674. .release = mxl5007t_release,
  675. .get_if_frequency = mxl5007t_get_if_frequency,
  676. };
  677. static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
  678. {
  679. char *name;
  680. int ret;
  681. u8 id;
  682. ret = mxl5007t_read_reg(state, 0xd9, &id);
  683. if (mxl_fail(ret))
  684. goto fail;
  685. switch (id) {
  686. case MxL_5007_V1_F1:
  687. name = "MxL5007.v1.f1";
  688. break;
  689. case MxL_5007_V1_F2:
  690. name = "MxL5007.v1.f2";
  691. break;
  692. case MxL_5007_V2_100_F1:
  693. name = "MxL5007.v2.100.f1";
  694. break;
  695. case MxL_5007_V2_100_F2:
  696. name = "MxL5007.v2.100.f2";
  697. break;
  698. case MxL_5007_V2_200_F1:
  699. name = "MxL5007.v2.200.f1";
  700. break;
  701. case MxL_5007_V2_200_F2:
  702. name = "MxL5007.v2.200.f2";
  703. break;
  704. case MxL_5007_V4:
  705. name = "MxL5007T.v4";
  706. break;
  707. default:
  708. name = "MxL5007T";
  709. printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
  710. id = MxL_UNKNOWN_ID;
  711. }
  712. state->chip_id = id;
  713. mxl_info("%s detected @ %d-%04x", name,
  714. i2c_adapter_id(state->i2c_props.adap),
  715. state->i2c_props.addr);
  716. return 0;
  717. fail:
  718. mxl_warn("unable to identify device @ %d-%04x",
  719. i2c_adapter_id(state->i2c_props.adap),
  720. state->i2c_props.addr);
  721. state->chip_id = MxL_UNKNOWN_ID;
  722. return ret;
  723. }
  724. struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
  725. struct i2c_adapter *i2c, u8 addr,
  726. struct mxl5007t_config *cfg)
  727. {
  728. struct mxl5007t_state *state = NULL;
  729. int instance, ret;
  730. mutex_lock(&mxl5007t_list_mutex);
  731. instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
  732. hybrid_tuner_instance_list,
  733. i2c, addr, "mxl5007t");
  734. switch (instance) {
  735. case 0:
  736. goto fail;
  737. case 1:
  738. /* new tuner instance */
  739. state->config = cfg;
  740. mutex_init(&state->lock);
  741. if (fe->ops.i2c_gate_ctrl)
  742. fe->ops.i2c_gate_ctrl(fe, 1);
  743. ret = mxl5007t_get_chip_id(state);
  744. if (fe->ops.i2c_gate_ctrl)
  745. fe->ops.i2c_gate_ctrl(fe, 0);
  746. /* check return value of mxl5007t_get_chip_id */
  747. if (mxl_fail(ret))
  748. goto fail;
  749. break;
  750. default:
  751. /* existing tuner instance */
  752. break;
  753. }
  754. if (fe->ops.i2c_gate_ctrl)
  755. fe->ops.i2c_gate_ctrl(fe, 1);
  756. ret = mxl5007t_soft_reset(state);
  757. if (fe->ops.i2c_gate_ctrl)
  758. fe->ops.i2c_gate_ctrl(fe, 0);
  759. if (mxl_fail(ret))
  760. goto fail;
  761. if (fe->ops.i2c_gate_ctrl)
  762. fe->ops.i2c_gate_ctrl(fe, 1);
  763. ret = mxl5007t_write_reg(state, 0x04,
  764. state->config->loop_thru_enable);
  765. if (fe->ops.i2c_gate_ctrl)
  766. fe->ops.i2c_gate_ctrl(fe, 0);
  767. if (mxl_fail(ret))
  768. goto fail;
  769. fe->tuner_priv = state;
  770. mutex_unlock(&mxl5007t_list_mutex);
  771. memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
  772. sizeof(struct dvb_tuner_ops));
  773. return fe;
  774. fail:
  775. mutex_unlock(&mxl5007t_list_mutex);
  776. mxl5007t_release(fe);
  777. return NULL;
  778. }
  779. EXPORT_SYMBOL_GPL(mxl5007t_attach);
  780. MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
  781. MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
  782. MODULE_LICENSE("GPL");
  783. MODULE_VERSION("0.2");